Patents by Inventor Li Yang

Li Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250144801
    Abstract: A manipulator execution path planning method for a complex space guided measurement task, includes: determining a measurement space of a manipulator and a starting point and a target point of a path; determining an obstructed space and a free space of the measurement space and a proportion of the obstructed space in the measurement space using a collision algorithm, and classifying and constructing a space compression model according to the proportion of the obstructed space in the measurement space to compress the measurement space and remove an invalid space; finding candidate paths for connecting the starting point and the target point by constructing an adjacent node tree connected topology network; finding a required path in the candidate paths, and performing high-order curve fitting to obtain a final path; discretizing the final path, and solving joint angles of the manipulator to obtain a joint track.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicant: China Jiliang University
    Inventors: Zai LUO, Wensong JIANG, Yan WANG, Li YANG, Minyue LI, Dian BIAN, Yaru LI
  • Publication number: 20250149070
    Abstract: A circuit includes a power management circuit configured to receive a first or second control signal, and to supply a first, second or third supply voltage. The power management circuit includes a first level shifter circuit, a first header circuit and a latch circuit. The first level shifter circuit is configured to generate a fourth control signal in response to a fifth control signal. The fourth control signal is a level shifted version of the fifth control signal. The first header circuit is configured to supply a first supply voltage of a first voltage supply to a first node in response to the first control signal, or a second supply voltage of a second voltage supply to a second node in response to a first level shifted signal. The latch circuit is configured to generate a first output control signal in response to the first and the fourth control signal.
    Type: Application
    Filed: January 7, 2025
    Publication date: May 8, 2025
    Inventors: Xiu-Li YANG, Ching-Wei WU, He-Zhou WAN, Ming-En BU
  • Publication number: 20250150137
    Abstract: Sending methods for an assistance communication device, communication apparatuses, and storage mediums are provided. The method includes: obtaining indication information for the assistance communication device, where the indication information includes at least one of channel state information (CSI) or a sending scheme; and executing precoding for the assistance communication device based on the indication information, to implement transceiving of signals.
    Type: Application
    Filed: February 15, 2022
    Publication date: May 8, 2025
    Applicant: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Liangang CHI, Li YANG
  • Publication number: 20250147518
    Abstract: An autonomous environmental perception, path planning and dynamic landing method includes: obtaining three-dimensional environment information in real time; determining a global starting point and a global end point, and generating an initial path; optimizing the initial path based on a local path optimization algorithm to obtain a first optimized path; when a perception threshold of the current position of the unmanned aerial vehicle is greater than a preset threshold, optimizing the initial path based on a frontier-perceived path optimization method to obtain a second optimized path and a local end point; when the unmanned aerial vehicle advances to the local end point, switching to optimizing the initial path in real time based on the local path optimization algorithm; and when the unmanned aerial vehicle arrives at the global end point, carrying out dynamic landing based on a deep reinforcement learning algorithm.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Applicant: China Jiliang University
    Inventors: Wensong JIANG, Zai LUO, Linzhen SHI, Jie ZHU, Li YANG, Minyue LI, Yaru LI, Dian BIAN, Yaxiong HE
  • Publication number: 20250141084
    Abstract: A transparent antenna is provided. A transparent antenna includes a transparent dielectric substrate, a plurality of antenna conductive layers, a feeding layer and a plurality of grounding layers. The antenna conductive layers are disposed on a first surface of the transparent dielectric substrate. The feeding layer is disposed on the first surface of the transparent dielectric substrate and is connected to the antenna conductive layers. Each of the antenna conductive layer, the feeding layer and the grounding layer is a mesh structure. The antenna conductive layers and the grounding layers corresponding thereto form a plurality of antenna units. The antenna conductive layers of the antenna units are not all the same; or the grounding layers of the antenna units are not all the same.
    Type: Application
    Filed: October 21, 2024
    Publication date: May 1, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Yang TSAI, Bing-Hsun LI, Kuang-Hui SHIH, Yu-Ching LIN
  • Patent number: 12286988
    Abstract: A rectifier and a flowmeter, the rectifier including a fairing, wherein a first rectifying section (1) positioned at the upstream, a reducing section (2) positioned at the midstream and a second rectifying section (3) positioned at the downstream, can be arranged in the fairing. The first rectifying section and the second rectifying section are respectively provided with a group of rectifying channels parallel to the flow direction of fluid, and a through-hole (21) can be formed in the reducing section. The rectifier can provide improved rectification effects.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 29, 2025
    Assignee: Honeywell International Inc.
    Inventors: Rui Liu, Wen Peng, Dong Luo, Li Yang
  • Patent number: 12289644
    Abstract: Systems and methods for wireless communications are disclosed herein. In one embodiment, a master node (MN) determines that a candidate target PScell/SCG in a candidate target secondary node (SN) needs to be released, canceled, or deleted. The candidate target SN is involved in a conditional SN addition or change multi-RAT dual connectivity (MR-DC) procedure of a wireless communication device. The MN and a source SN are currently configured to provide communication services to the wireless communication device. The MN requests to release, cancel, or delete the at least one candidate target PScell/SCG in the candidate target SN using a first signaling procedure.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: April 29, 2025
    Assignee: ZTE Corporation
    Inventor: Li Yang
  • Publication number: 20250127963
    Abstract: An injectable hydrogel for heart failure treatment with myocardial tissue repair function and its preparation method and use are disclosed. The hydrogel is prepared by chelating alginic acid and multivalent cations. The hydrogel is loaded with an active substance for repairing cardiac injury. The active substance is recombinant humanized collagen type III. The hydrogel is administrated into the left ventricle free wall by transendocardial injection. Implanting the hydrogel in the myocardium can increase the thickness of the left ventricular wall, adjust the stress of the ventricular wall, affect the morphology of the left ventricle, and prevent or reverse left ventricular enlargement. Further, the hydrogel is loaded with a new recombinant humanized collagen material that has the function of repairing cardiac tissue injury to further improve cardiac function and promote cardiac repair.
    Type: Application
    Filed: October 28, 2024
    Publication date: April 24, 2025
    Inventors: Yunbing Wang, Li Yang, Nan Shao, Xia Yang, Xingdong Zhang
  • Publication number: 20250121096
    Abstract: The present invention relates to engineered liver-specific enhancers, synthetic promoters containing the enhancers, expression vectors containing the synthetic promoters, as well as methods of using the enhancer or the expression vector thereof to address the need in the field, such as treatment of various genetic diseases or conditions associated with the liver. In some embodiments, the engineered enhancer comprises one or more DNA binding sites for transcription factors.
    Type: Application
    Filed: October 17, 2024
    Publication date: April 17, 2025
    Applicant: Sichuan Real&Best Biotech Co., Ltd.
    Inventors: Biao Dong, Li Yang
  • Patent number: 12278573
    Abstract: Provided is a friction nano power generation synaptic transistor. The friction nano power generation synaptic transistor includes a friction nano generator, a synaptic transistor, a substrate, an electrode layer formed on the substrate, a shared intermediate layer formed on the electrode layer; a synaptic transistor active layer, a source electrode, and a drain electrode which are formed on the shared intermediate layer; and a positive friction layer and a negative friction layer formed on the shared intermediate layer, where the shared intermediate layer is used as a dielectric layer of the synaptic transistor and an intermediate layer of the friction nano generator.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: April 15, 2025
    Assignee: XI'AN JIAOTONG-LIVERPOOL UNIVERSITY
    Inventors: Qihan Liu, Chun Zhao, Cezhou Zhao, Yina Liu, Li Yang
  • Publication number: 20250118346
    Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
  • Publication number: 20250111072
    Abstract: The described embodiments set forth techniques for managing digital media item delivery queues associated with a user and/or with a user device. The techniques provide a framework for establishing and subsequently modifying or limiting access to an allocation for digital media items managed via a digital media item delivery queue associated with a user and/or a user device. In some cases, a user and/or user device is allowed limited access to a digital media item delivery queue allocation, while a negative status for a previously provided digital media item is unresolved, based on a set of limited access criteria being satisfied. Exemplary limited access criteria include an account standing for a user of the user device or a type of digital media item request, e.g., a subscription renewal or modification to a current, ongoing subscription for the user device or a user thereof, and the like.
    Type: Application
    Filed: June 19, 2024
    Publication date: April 3, 2025
    Inventors: Yuvraj S. NEGI, Jonathan W. REIHER, Bagath S. PUGAZHENDHI, David L. NEUMANN, Li Yang LEE, Dylan A. EYSTER, Hannah M. JACKSON, Madhusudan RAO, Merlyne G. MICHAEL, Michael C. OKOLO, Na TIAN, Samiran ADAK, Win M. HTAY, Yichen LIU
  • Patent number: 12266593
    Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Li Yang, Wen-Hsiung Lu, Jhao-Yi Wang, Fu Wei Liu, Chin-Yu Ku
  • Publication number: 20250106605
    Abstract: Management and coordination of sensing may be performed through a wireless sensing session management function (S-SMF) that provides policies, configuration data, or sensing assistant data related to a wireless sensing session. S-SMF may be in independent and decoupled from a session management function (SMF), which provides communication session related policies and configuration data. The S-SMF manages the wireless sensing session and the SMF manages other communication sessions. Additional functions may include a Sensing Anchor Function (AMF) configured for controlling a wireless sensing session, and a Sensing Data Storage Function (S-UPF) configured for storing wireless sensing result data from the wireless sensing session.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 27, 2025
    Applicant: ZTE Corporation
    Inventors: Li YANG, Zhiqiang HAN, Shuqiang XIA, Feng XIE
  • Publication number: 20250101051
    Abstract: Aspects of the disclosure relate to methods for producing organotin compounds with high purity, which may involve the use of specific additives or reaction conditions. Methods for purifying organotin compounds and suppressing the formation of impurities in organotin compounds are also described.
    Type: Application
    Filed: September 5, 2024
    Publication date: March 27, 2025
    Inventors: Li Yang, Thao Nguyen, Koki Ishii, Yuta Hioki, Koki Matsuzaka
  • Publication number: 20250107222
    Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Li-Yang CHUANG, Jia-Chuan YOU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250104766
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20250104765
    Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Patent number: 12260972
    Abstract: Provided are a micro-nano wire manufacturing device and a micro-nano structure. The micro-nano wire manufacturing device includes a liquid-phase nanomaterial storage device and a micro-nano wire applying mechanism. The liquid-phase nanomaterial storage device is provided with a liquid outlet. The micro-nano wire applying mechanism is provided in one-to-one correspondence with the liquid outlet. The micro-nano wire applying mechanism includes at least two flexible wires. The roots of the flexible wires are secured to the liquid-phase nanomaterial storage device. One ends of the two flexible wires hang down to a substrate and abut against each other. The range of the angle between the projections of the two flexible wires on the substrate is 1° to 5°.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: March 25, 2025
    Assignee: XI'AN JIAOTONG-LIVERPOOL UNIVERSITY
    Inventors: Yuxiao Fang, Chun Zhao, Cezhou Zhao, Li Yang
  • Publication number: 20250098139
    Abstract: A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Yan-Bo SONG