Abstract: Embodiments of the invention are directed to computer-implemented methods of analyzing a web-based software application. A non-limiting example of the computer implemented method includes generating, using a processor system, a set of to-be-tested element-event pairs of the web-based software application. A set of compatibility tests is received at the processor system, where the set of compatibility tests is operable to perform compatibility testing of a corresponding set of element-event pairs. A comparison is performed between the set of to-be-tested element-event pairs and the corresponding set of element-event pairs. A compatibility testing recommendation is generated based at least in part on a result of the comparison.

Abstract: A computer-implemented method for matching material names from one or more material sources with safety data sheet material names from one or more safety data sheets. The method includes: extracting the material names from the one or more material sources; preprocessing the material names and removing extraneous data from one or more of the material names; selecting one of the material names; comparing the selected material name with the safety data sheet material names; identifying the safety data sheet material names that match the material name; and transmitting an output to a user device to display the material name and the matching safety data sheet material names.

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

Abstract: A display device and a manufacturing method thereof, an electronic device, and a light control panel are provided. The display device includes a light control panel and a display liquid crystal panel. The display liquid crystal panel is on a light-emitting side of the light control panel; the light control panel includes a light control region, and the light control region is configured to provide adjusted backlight to the display liquid crystal panel; the display liquid crystal panel includes a display region, and the display region is configured to receive the adjusted backlight to perform display; and a distance between two opposite edges of the light control region in at least one direction is greater than a distance between two opposite edges of the display region in the at least one direction.

Abstract: Methods and apparatus for interference discovery for simultaneous transmission and reception are provided. In an embodiment, a station (STA) receives a STR request message from an access point (AP). The STA transmits a first STR response message to the AP based on the received STR request message. The STA receives a second STR response message transmitted from a second STA to the AP. The STA determines a received power of the received second STR response message. The STA receives a first trigger message from the AP. The first trigger message indicates a STA role field. The STA transmits interference information to the AP. The interference information is based on the determined received power. The STA role field comprises an indication of at least one or more of a primary STA and a secondary STA. The STA aggregates the interference report with a data transmission to the AP in response to the first trigger message.

Abstract: A system information transmission method, a terminal and a network device are provided. The method includes: receiving request information for requesting target Other System Information sent by a terminal; configuring a random access message 2 or a random access message 4 for the terminal based on the request information; and sending the random access message 2 or the random access message 4 to the terminal.

Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.

Abstract: At least one processor identifies dependency relationships among libraries in a repository of libraries. Using the dependency relationships among libraries, at least one machine learning model can be created that predicts with a confidence value a dependency between a given library and a target library. An L layer tree-like graph can be created, using the dependency relationships among libraries and an application package. L can be configurable. Versions of the libraries to use can be determined by running the at least one machine learning model for each pair of nodes having a dependency relationship in the L layer tree-like graph, the at least one machine learning model identifying the dependency relationship with a confidence value, where pairs of nodes having largest confidence values are selected as the versions of the libraries to use in the application package.

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

Abstract: A digital microfluidic apparatus and a driving method therefor. The digital microfluidic apparatus comprises a digital microfluidic chip (10), a thermal control apparatus (20), and an elastic support apparatus (30). The digital microfluidic chip (10) is provided with a droplet channel (91), and the droplet channel (91) is configured to allow droplets (90) to move therein; the thermal control apparatus (20) is disposed on one side of the digital microfluidic chip (10), and is configured to generate at least two independent and non-interference hot zones in the droplet channel (91), and control the temperature of each hot zone; and the elastic support apparatus (30) is disposed on the side of the thermal control apparatus (20) away from the digital microfluidic chip (10), and is configured to drive the thermal control apparatus (20) to be pasted on the surface of the digital microfluidic chip (10).

Abstract: In a communication method, a session management function network element initiates a procedure of a first operation for a first session; the session management function network element receives a request to establish user-plane resources for the first session from an access and mobility management function network element in a process of performing the first operation; and the session management function network element determines a subsequent procedure based on the first operation.

Abstract: The present disclosure relates to a rotary vane vacuum pump 300 (300?) comprising a gas ballast assembly 330. The gas ballast assembly 330 comprises a gas ballast passage fluidly connected to a stator chamber 212 of the pump 300, a gas ballast valve 334 configured to selectively open and close the gas ballast passage depending on the relative gas pressure across the valve 334, and a gas ballast buffer chamber 360 fluidly connected to the gas ballast passage upstream of the gas ballast valve 343, which is in selective fluid communication with the exterior of the pump 300 (300?). The present disclosure also provides a related method of communicating ballast gas to a rotary vane vacuum pump 300 (300?).

Abstract: A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside via.

Abstract: A process for producing a barrier composition includes subjecting a siloxane compound having 1 to 3 amino groups and an aqueous solution including water and an alcohol to hydrolysis and first-stage condensation under required conditions, subjecting a first colloidal mixture obtained and an additional alcohol to second-stage condensation, subjecting a second colloidal mixture obtained, which has a particular solid content, to heating under required conditions, and subjecting a cured product obtained to aging under required conditions. A barrier composition produced by the process is also disclosed.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.