Patents by Inventor Li Zhao

Li Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10355891
    Abstract: Embodiments may include systems and methods for authenticating a message between a transmitter and a receiver. An apparatus for communication may include a transmitter to transmit a message to a receiver via a physical channel coupling the transmitter and the receiver. The message may be transmitted via a plurality of transmission voltage levels varied from a plurality of nominal voltage levels on the physical channel. The transmitter may include a voltage generator to generate the plurality of transmission voltage levels varied in accordance with a sequence of voltage variations from the plurality of nominal voltage levels for the message. The sequence of voltage variations may serve to authenticate the message between the transmitter and the receiver. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Marcio Juliato, Li Zhao, Ahmed Shabbir, Manoj R. Sastry, Santosh Ghosh, Rafael Misoczki
  • Patent number: 10348495
    Abstract: Apparatuses and methods associated with configurable crypto hardware engine are disclosed herein. In embodiments, an apparatus for signing or verifying a message may comprise: a hardware hashing computation block to perform hashing computations; a hardware hash chain computation block to perform successive hash chain computations; a hardware private key generator to generate private keys; and a hardware public key generator to generate public keys, including signature generations and signature verifications. The hardware hashing computation block, the hardware hash chain computation block, the hardware private key generator, and the hardware public key generator may be coupled to each other and selectively cooperate with each other to perform private key generation, public key generation, signature generation or signature verification at different points in time. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Rafael Misoczki, Manoj R. Sastry, Li Zhao
  • Patent number: 10341116
    Abstract: An attestation protocol between a prover device (P), a verifier device (V), and a trusted third-party device (TTP). P and TTP have a first trust relationship represented by a first cryptographic representation based on a one-or-few-times, hash-based, signature key. V sends an attestation request to P, with the attestation request including a second cryptographic representation of a second trust relationship between V and TTP. In response to the attestation request, P sends a validation request to TTP, with the validation request being based on a cryptographic association of the first trust relationship and the second trust relationship. TTP provides a validation response including a cryptographic representation of verification of validity of the first trust relationship and the second trust relationship. P sends an attestation response to V based on the validation response.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Xiruo Liu, Rafael Misoczki, Manoj R Sastry, Santosh Ghosh, Li Zhao
  • Patent number: 10326587
    Abstract: A cryptography accelerator system includes a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and an on-the-fly hashing circuit to hash data read from a first memory circuit on-the-fly before writing the read data to a second memory circuit. The hashing circuit performs at least one of integrity protection and firmware/software (FW/SW) verification of the data prior to writing the data to the second memory circuit. The on-the-fly hashing circuit includes a bit repositioning circuit to designate an order of bits of a binary word in a register from a most significant bit (MSB) to a least significant bit (LSB) for performing computations without rotating bits in the register, and an on-the-fly round constant generator circuit to generate a round constant from a counter.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Li Zhao, Rafael Misoczki, Manoj R Sastry
  • Patent number: 10313486
    Abstract: The present invention increases the efficiency of transmitting data from a plurality of fragmented internet protocol (IP) packets over a computer network. After receiving a plurality of fragmented packets over a computer network interface a computing device may reassemble data from the plurality of packets into an IP packet that includes data from each of the fragmented IP packets. The reassembled IP packet may then be compressed and encrypted before being transmitted to a computer identified in a destination address in each of the plurality of fragmented packets.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 4, 2019
    Assignee: SONICWALL INC.
    Inventors: Li Zhao, Dong Xiang, Zhong Chen, Yicheng He, Yanjun Yang
  • Patent number: 10313130
    Abstract: One embodiment provides a signer device. The signer device includes hash signature control logic and signer signature logic. The hash signature control logic is to retrieve a first nonce, to concatenate the first nonce and a message to be transmitted and to determine whether a first message representative satisfies a target threshold. The signer signature logic is to generate a first transmitted signature based, at least in part, on the first message representative, if the first message representative satisfies the target threshold. The hash signature control logic is to retrieve a second nonce, concatenate the second nonce and the message to be transmitted and to determine whether a second message representative satisfies the target threshold, if the first message representative does not satisfy the target threshold.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Rafael Misoczki, Steffen Schulz, Manoj R. Sastry, Santosh Ghosh, Li Zhao
  • Publication number: 20190116569
    Abstract: Embodiments of the present disclosure provide a method and a device for identifying a synchronization priority, including: determining a synchronization priority of a node according a connection relationship between the node and a Global Navigation Satellite System (GNSS) and a relative relationship between the node and a coverage scope of an eNB; configuring a synchronization sequence and an in coverage flag of the node according to the synchronization priority of the node. Combination of the synchronization sequence and the in coverage flag of the node is used to identify the synchronization priority of the node.
    Type: Application
    Filed: March 31, 2017
    Publication date: April 18, 2019
    Applicant: CHINA ACADEMY OF TELECOMMUNICATIONS TECHNOLOGY
    Inventors: Li ZHAO, Yuanyuan LI, Haijun ZHOU, Rui ZHAO, Ying PENG, Jiayi FANG
  • Publication number: 20190101776
    Abstract: Disclosed is a liquid crystal display panel, comprising an array substrate and a common voltage compensation circuit. The array substrate comprises scan lines, data lines, common electrode lines and sub pixel units arranged in array. The scan lines provide driving voltages to the sub pixel units, and the data lines provide data voltages to the sub pixel units, and the common electrode lines provide common voltages to the sub pixel units. The common voltage compensation circuit comprises a feedback signal processor, an amplifier and a common voltage adjusting circuit, and the feedback signal processor is connected to the common electrode lines to obtain feedback signals of the common voltages, and the amplifier implements an amplifying process to the feedback signals after inversion to obtain compensation signals, and the common voltage adjusting circuit inputs the compensation signals to the common electrode lines.
    Type: Application
    Filed: May 10, 2017
    Publication date: April 4, 2019
    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Li ZHAO
  • Publication number: 20190104001
    Abstract: Embodiments may include systems and methods for authenticating a message between a transmitter and a receiver. An apparatus for communication may include a transmitter to transmit a message to a receiver via a physical channel coupling the transmitter and the receiver. The message may be transmitted via a plurality of transmission voltage levels varied from a plurality of nominal voltage levels on the physical channel. The transmitter may include a voltage generator to generate the plurality of transmission voltage levels varied in accordance with a sequence of voltage variations from the plurality of nominal voltage levels for the message. The sequence of voltage variations may serve to authenticate the message between the transmitter and the receiver. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Marcio Juliato, Li Zhao, Ahmed Shabbir, Manoj R. Sastry, Santosh Ghosh, Rafael Misoczki
  • Publication number: 20190099698
    Abstract: The present disclosure discloses an impacting T-junction component regulator for regulating components of a non-azeotropic working medium, which is formed by connecting a single T-junction or a plurality of T-junctions. Each of the T-junction comprises an inlet pipe and an outlet pipe. When the impacting T-junction component regulator is formed by a plurality of connected T-junctions, the impacting T-junction component regulator further comprises an upper manifold trunk communicated with an outlet pipe of each T-junction and throttle valves located between two adjacent T-junctions. By using the characteristics of unequal vapor and liquid components of the non-azeotropic working medium and mal-distribution of two phase flows by vertical impacting T-junctions, the regulator achieves the fluid flowing through a plurality of T-junctions and throttle valves once so as to achieve the purpose of separating components.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 4, 2019
    Inventors: Li ZHAO, Wen SU, Nan ZHENG, Shuai DENG, Pei LU
  • Publication number: 20190069255
    Abstract: Disclosed are a synchronization method and apparatus, used for implementing a specific synchronization solution when a terminal node serves as a synchronization source. The synchronization method provided in the present application comprises: determining, when synchronization signals of a plurality of nodes are received, synchronization priorities of the plurality of nodes; and selecting, according to the synchronization priorities of the plurality of nodes, a synchronization signal of one of the nodes for synchronization.
    Type: Application
    Filed: January 20, 2017
    Publication date: February 28, 2019
    Applicant: China Academy of Telecommunications Technology
    Inventors: Li ZHAO, Haijun ZHOU, Ying PENG, Yuanyuan LI, Jiayi FANG
  • Patent number: 10215748
    Abstract: Use of impedance devices in methods of generating a time dependent cellular profiles (TCRP) for the modulation of oncogene addicted cells and comparing the impedance-based TCRP to controls or knowns to identify signature time dependent cellular profiles.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: February 26, 2019
    Assignee: ACEA Biosciences, Inc.
    Inventors: Yama A. Abassi, Li Zhao, Ning Ke, Xiaobo Wang, Xiao Xu
  • Publication number: 20190042738
    Abstract: Methods and apparatus relating to a physics-based approach for attack detection and/or localization in closed-loop controls for autonomous vehicles are described. In an embodiment, multiple state estimators are used to compute a set of residuals to detect, classify, and/or localize attacks. This allows for determination of an attacker's location and the kind of attack being perpetrated. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 28, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: MARCIO JULIATO, SHABBIR AHMED, MANOJ SASTRY, LIUYANG L. YANG, VUK LESI, LI ZHAO
  • Publication number: 20190044912
    Abstract: There is disclosed in one example a computing apparatus, including: a hardware platform; a network interface to communicatively couple to a bus lacking native support for authentication; and an anomaly detection engine to operate on the hardware platform and configured to: receive a first data stream across a first time; symbolize and approximate the first data stream, including computing a first window sum; receive a second data stream across a second time substantially equal in length to the first time, the second data stream including data across the plurality of dimensions from the first data stream; symbolize and approximate the second data stream, including computing a second window sum; compute a difference between the first window sum and the second window sum; determine that difference exceeds a threshold and that the correlation across the plurality of dimensions is broken; and flag a potential anomaly.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Liuyang Lily Yang, Huaxin Li, Li Zhao, Marcio Juliato, Shabbir Ahmed, Manoj R. Sastry
  • Publication number: 20190037510
    Abstract: Disclosed are a synchronization method and device, which are used to achieve the distinction of a synchronization system and a synchronization level of a node in a V2V communication system, thereby quickly achieving the synchronization in the V2V communication system. Provided is a synchronization method, comprising: determining a synchronization priority level of a current node; and according to the synchronization priority level of the current node, determining a synchronization sequence used by the current node and a value of a distinguishing flag bit of the current node, wherein the distinguishing flag bit is used to distinguish whether the current node belongs to a GNSS synchronization system or an eNB synchronization system.
    Type: Application
    Filed: January 11, 2017
    Publication date: January 31, 2019
    Inventors: Yuanyuan LI, Haijun ZHOU, Li ZHAO, Ying PENG, Jiayi FANG
  • Publication number: 20190007915
    Abstract: Methods are directed towards initializing a path maximum transmission unit value for two gateways in communication via a network tunnel (e.g., VPN environment). The initialized path maximum transmission unit value is used in establishing the network tunnel of the two gateways. Methods are also directed towards synchronizing path maximum transmission unit values for the two gateways after the network tunnel has been established. These methods minimize the occurrence of dropped data packets arising from mismatched path maximum transmission unit value between the gateways.
    Type: Application
    Filed: May 22, 2018
    Publication date: January 3, 2019
    Inventors: Dong Xiang, Yicheng He, Yanjun Yang, Li Zhao
  • Patent number: 10124764
    Abstract: Various systems and methods for intrusion detection are described herein. An electronic device for intrusion detection includes memory circuitry to store a set of signature voltage ratios and a corresponding set of node identifiers, each node identifier corresponding to a unique signature voltage ratio; and security circuitry to: compare voltages received at a first and second measuring point on a bus, the voltages resulting from a message transmitted by a sending node on the bus, the first measuring point providing a first voltage and the second measuring point providing a second voltage; calculate a test voltage ratio from the first voltage and the second voltage; determine whether the test voltage ratio is in the set of signature voltage ratios; and initiate a security response based on whether the test voltage ratio is in the set of signature voltage ratios.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Shabbir Ahmed, Marcio Rogerio Juliato, Li Zhao, Manoj R. Sastry
  • Publication number: 20180310296
    Abstract: The present disclosure provides in some embodiments a resource scheduling method and a resource scheduling device for a vehicle infrastructure cooperative communication system, and a node of the vehicle infrastructure cooperative communication system. According to the present disclosure, a movement trend between nodes is determined in accordance with node position information, so as to spatially multiplex time-frequency resources and prevent the frequent adjustment of time-frequency resources, thereby to reduce signaling overhead for allocating the time-frequency resources and improve utilization of the time-frequency resources.
    Type: Application
    Filed: November 4, 2016
    Publication date: October 25, 2018
    Applicant: CHINA ACADEMY OF TELECOMMUNICATIONS TECHNOLOGY
    Inventors: Li ZHAO, Jiye TANG, Jiayi FANG, Yuan FENG, Lin LIN
  • Patent number: 10111192
    Abstract: Methods are directed towards initializing a path maximum transmission unit value for two gateways in communication via a network tunnel (e.g., VPN environment). The initialized path maximum transmission unit value is used in establishing the network tunnel of the two gateways. Methods are also directed towards synchronizing path maximum transmission unit values for the two gateways after the network tunnel has been established. These methods minimize the occurrence of dropped data packets arising from mismatched path maximum transmission unit value between the gateways.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: October 23, 2018
    Assignee: SONICWALL INC.
    Inventors: Dong Xiang, Yicheng He, Yanjun Yang, Li Zhao
  • Patent number: 10082708
    Abstract: The present disclosure discloses a liquid crystal panel and a liquid crystal device. The liquid crystal panel includes a thin film transistor (TFT) substrate and a color filter (CF) substrate opposite to each other. Each of sub-pixel areas of the TFT substrate is configured with a first conductive film, and each of sub-optical-filter areas of the CF substrate is configured with a second conductive film opposite to the first conductive film, the first conductive film and the second conductive film are rectangular. A central point of the first conductive film projects on the central point of the second conductive film. A dimension of the second conductive film is greater than the dimension of the first conductive film, and a ring-shaped conductive film is formed in an area of the first conductive film not covered by the second conductive film.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: September 25, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Li Zhao, Bangyin Peng