Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: The present invention provides a supporting hook structure, comprising a sleeve, a fixing rod, a first limit unit, a hook and a fixing device. The fixing rod is connected to the side surface of the sleeve. The hook body is connected to one end of the sleeve. The first limit unit is arranged on the side surface of the sleeve and adjacent to the hook body. The first limit unit makes the hook body rotates with the axis direction of the sleeve as a rotation axis. The fixing device is connected to the other end of the sleeve to fix the rotating position of the hook body. Through the above, the hook part enters the proximal thigh from a surgical entrance and the hook part rotates to make the hook part abut against the proximal femur to complete the positioning and fixation of the femur hook structure to the femur.

Abstract: Provided are a fibroblast activation protein inhibitor (FAPI) dimer compound, an FAPI dimer-based positron emission tomography (PET) imaging agent for tumor diagnosis, and a preparation method and use thereof. An amphiphilic polyethylene glycol (PEG) chain and a dimerized structure of FAPI in the FAPI dimer compound with a structure shown in formula I can improve the in vivo kinetic properties of the compound and prolong a residence time of the compound in a tumor, thereby improving the uptake and imaging effects in the tumor. The accurate tumor diagnosis can be achieved by labeling the FAPI dimer compound with a diagnostic nuclide (68Ga), which has promising application prospects in PET imaging for diagnosis and in the preparation of a therapeutic nuclide (such as 177Lu or 90Y)-labeled drug for treating a FAP-?-expressing tumor.

Abstract: An inspection system includes an excitation light source, a voltage-sensing film, an illumination light source, an image capture device. The excitation light source provides an excitation beam to light-emitting diodes to generate open-circuit voltages. The voltage-sensing film is at a top side of the light-emitting diodes and includes a voltage-sensing medium layer and a first electrode layer. The first electrode layer is in the voltage-sensing medium layer to provide a gain effect of the open-circuit voltages, so that the voltage-sensing medium layer senses the open-circuit voltages, and a display of the voltage-sensing medium layer is changed with a portion or all of the open-circuit voltages. The illumination light source provides an illumination beam to the voltage-sensing film to generate a sensing image according to a display change. The image capture device is on a transmission path of the sensing image and receives the sensing image to generate an inspection result.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE sends a request message to a core network. The request message requests joining one or more requested multicast broadcast service (MBS) sessions. The UE receives a response message from the core network. The response message contains received MBS information indicating one or more admitted MBS sessions. The received MBS information includes a respective IP address type (IPAT) field. The IPAT field indicates a type of an IP address corresponding to each of the one or more admitted MBS sessions. The UE decodes the IP address corresponding to each of the one or more admitted MBS sessions according to the type indicated by the respective IPAT field.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A backlight module including a light guide plate, a light source, a diffuse reflector and a light-splitting film is provided. The light guide plate has a light incident surface, and a light-emitting surface and a bottom surface which are respectively connected to the light incident surface and opposite to each other. The light source is disposed on one side of the light incident surface of the light guide plate. The diffuse reflector is disposed on one side of the bottom surface of the light guide plate. The light-splitting film is disposed between the light guide plate and the diffuse reflector. The light-splitting film has a substrate and a plurality of first optical microstructures disposed on one side of the substrate. An extending direction of the first optical microstructures intersects with the light incident surface of the light guide plate. A display apparatus using the backlight module is also provided.

Abstract: A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.

Abstract: A door lock includes a latch driving device having a thumb turn that can be switched between a locking position not permitting movement of a latch to an unlatching position when an outer handle is pivoted and an unlocking position permitting movement of the latch to unlatching position when the outer handle is pivoted. The thumb turn includes an actuator controlling a switch to a conductive state or a non-conductive state. When the thumb turn is in the locking position, the switch is in the conductive state, and a lighting element controlled by the switch generates light transmitting through the first lid. When the thumb turn is in the unlocking position, the switch is in the non-conductive state, and the lighting element does not generate light. Thus, the locking or unlocking state of the door lock can be identified by sight.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: A sample rack recovery method after an accidental interruption of operation of a sample rack manipulation device (10), a sample rack manipulation device (10) capable of performing the method, an automatic detection system (1) comprising the device (10), and a computer-readable medium in which a program for executing the method is stored. The device (10) comprises a conveying device (103) adapted to move in a transport area (TB) to convey a sample rack (30) between a loading/unloading area (TA), sampling areas (TD, TE) and a buffer area (TC). The method comprises: a conveying device detection step of detecting the state of a conveying device (103); a sample rack detection step of detecting the position of a sample rack (30) in a sample rack manipulation device (10); and a sample rack recovery step of conveying the sample rack (30) to a loading/unloading area (TA) by the conveying device (103) according to the detection results of the conveying device (103) and the sample rack (30).

Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.

Abstract: A semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. The semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. The semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: Embodiments of this disclosure provide a method for starting an application and a related apparatus. The method includes the following: A user terminal may acquire a configuration parameter of a target application from a data management server when a start instruction for the target application is detected. The configuration parameter includes plugin configuration information and code package configuration information. The target application can be executed by using a target code package and a locally cached target plugin.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

Abstract: The physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. During a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. The physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. Additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.