Abstract: The present disclosure relates to a method of operating an OSD function for a public-place-device. The method includes: detecting a touch input through the touch screen while the OSD function is in the locked state; causing the OSD function to operate in the unlocked state in response to detecting a predetermined touch secret code, so as to output an OSD image on the display and conduct an OSD configuration of the display according to an OSD operation from an external entity; and causing the OSD function to operate in the locked state in response to receiving an OSD locking request while the OSD function is in the unlocked state, so as not to output the OSD image on the display and not to respond to an OSD operation from an external entity. The present disclosure also relates to an OSD system and a self-service device for the public-place-device.

Abstract: A method and a system for consolidating a subterranean formation are provided. An exemplary method includes injecting a water-in-oil emulsion into an unconsolidated subterranean formation, wherein the water-in-oil emulsion includes comonomers in an oil phase to form a polyurethane resin, and a catalyst in an aqueous phase. The method also includes allowing the polyurethane resin to cure to form a porous polymeric network.

Abstract: An electronic device display may have pixels formed from crystalline semiconductor light-emitting diode dies, organic light-emitting diodes, or other pixel structures. The pixels may be formed on a display panel substrate. A display panel may extend continuously across the display or multiple display panels may be tiled in two dimensions to cover a larger display area. Interconnect substrates may have outwardly facing contacts that are electrically shorted to corresponding inwardly facing contacts such as inwardly facing metal pillars associated with the display panels. The interconnect substrates may be supported by glass layers. Integrated circuits may be embedded in the display panels and/or in the interconnect substrates. A display may have an active area with pixels that includes non-spline pixels in a non-spline display portion located above a straight edge of the display and spline pixel in a spline display portion located above a curved edge of the display.

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: A semiconductor device includes a through-silicon via (TSV) in a TSV zone in a substrate and the TSV extends through the substrate; an ESD cell proximal to a first end of the TSV and in contact with the TSV zone, the ESD cell including a set of diodes electrically connected in parallel to each other; an antenna pad electrically connected to a second end of the TSV; and an antenna electrically connected to the antenna pad and extending in a first direction, the first direction is parallel to a major axis of the TSV. The semiconductor device includes a conductive pillar extending parallel to the TSV at a same side of the substrate as the antenna pad, wherein a first end of the conductive pillar electrically connects to the antenna pad, and a second end of the conductive pillar electrically connects to the set of diodes of the ESD cell.

Abstract: An optimization method for a mask pattern optical transfer includes steps as follows: First, a projection optical simulation is performed to obtain an optimal pupil configuration scheme corresponding to a virtual mask pattern. Next, a position scanning is performed to change the optimal pupil configuration scheme, so as to generate a plurality of adjusted pupil configuration schemes. A mask pattern transfer simulation is performed to obtain a plurality of pupil configuration schemes-critical dimension relationship data corresponding to the virtual mask pattern. Subsequently, an actual pupil configuration scheme suitable for an actual mask pattern is selected according to the plurality of pupil configuration schemes-critical dimension relationship data, and upon which an actual mask pattern transfer is performed.

Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

Abstract: A treatment fluid composition includes a carrier fluid and a curable hybrid resin. The curable hybrid resin includes a first curable resin (A) including a reactive silyl group that reacts with water downhole, a second curable resin (B), and a curing agent for the second curable resin (B). A method of treating a subterranean formation includes injecting a treatment fluid including a curable hybrid resin into a target zone of the subterranean formation. The target zone may have unconsolidated or weakly consolidated sand. The method then includes maintaining the treatment fluid in the target zone for a period of time such that the curable hybrid resin cures and forming a consolidated formation in the target zone.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.

Abstract: A method of transmitting data and command through an RS232 serial port incorporated with a user-end device and a server-end device connected through the RS232 serial port is disclosed and includes following steps: accumulating a value of a first counter of the user-end device and a value of a second counter of the server-end device whenever a data is transmitted from the server-end device to the user-end device; controlling the server-end device to stop transmitting the data and to wait when both of the two values reach a triggering threshold; controlling the user-end device to transmit a control command to the server-end device through the RS232 serial port while the server-end device is waiting; and, resetting the first and the second counter and controlling the server-end device to restore to transmit the data to the user-end device after a waiting time is elapsed.

Abstract: A video encoder with quality estimation is shown. The video encoder has a video compressor, a video reconstructor, a quality estimator, and an encoder top controller. The video compressor receives the source data of a video to generate compressed data. The video reconstructor is coupled to the video compressor for generation of playback-level data that is buffered for inter prediction by the video compressor, wherein the video reconstructor generates intermediate data and, based on the intermediate data, the video reconstructor generates playback-level data. The quality estimator is coupled to the video reconstructor to receive the intermediate data. Quality estimation is performed based on the intermediate data rather than the playback-level data. Based on the quality estimation result, the encoder top controller adjusts at least one video compression factor in real time.

Abstract: According to the present disclosure, a measuring method of liquid mixture purity includes steps as follows. A storage tank is provided, wherein the storage tank is configured for storing a liquid mixture including formic acid and water. A calculating unit is provided, wherein a plurality of formic acid purity values are saved in the calculating unit. A pressure-decreasing and heating step is performed by reducing a pressure of the storage tank and heating the storage tank. A measuring step is performed by measuring in the inner space of the storage tank to obtain a pressure value, and measuring the liquid mixture simultaneously to obtain a temperature value. A calculating step is performed by inputting the pressure value and the temperature value into the calculating unit, wherein the calculating unit outputs one of the formic acid purity values corresponding thereto.

Abstract: A treatment fluid composition includes a carrier fluid and a curable hybrid resin. The curable hybrid resin includes a first curable resin (A) including a reactive silyl group that reacts with water downhole, a second curable resin (B), and a curing agent for the second curable resin (B). A method of treating a subterranean formation includes injecting a treatment fluid including a curable hybrid resin into a target zone of the subterranean formation. The target zone may have unconsolidated or weakly consolidated sand. The method then includes maintaining the treatment fluid in the target zone for a period of time such that the curable hybrid resin cures and forming a consolidated formation in the target zone.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.