Patents by Inventor Liang Cheng

Liang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image processing method and terminal device, and system
    Patent number: 11783517
    Abstract: An image processing method includes obtaining a reflective picture, superimposing the reflective picture on an icon, and changing a color value of at least one pixel in a part that is of the reflective picture and that overlaps the icon.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 10, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Kang Li, Jun Liang, Liang Cheng
  • Gate Capping Structures In Semiconductor Devices
    Publication number: 20230317828
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang CHENG
  • Semiconductor device with contact structure
    Patent number: 11776900
    Abstract: A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • SYSTEM AND METHOD FOR DETECTING CONTAMINATION OF THIN-FILMS
    Publication number: 20230296523
    Abstract: A thin-film deposition system deposits a thin-film on a wafer. A radiation source irradiates the wafer with excitation light. An emissions sensor detects an emission spectrum from the wafer responsive to the excitation light. A machine learning based analysis model analyzes the spectrum and detects contamination of the thin-film based on the spectrum.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventor: Chung-Liang CHENG
  • Anti-curling film
    Patent number: 11760853
    Abstract: An anti-curling film is provided. The anti-curling film includes a first portion and a second portion covering the first portion. The first portion includes polylactic acid (PLA), polycaprolactone (PCL), polyethylene glycol dimethacrylate (PEGDMA) and a photoinitiator. The second portion includes polycaprolactone (PCL), gelatin, hyaluronic acid (HA), alginate (AA), polyvinyl alcohol (PVA) or a combination thereof.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: September 19, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Hong Chang, Ching-Mei Chen, Grace H. Chen, Hsin-Hsin Shen, Yuchi Wang, Ming-Chia Yang, Li-Hsin Lin, Sen-Lu Chen, Yi-Hsuan Lee, Jian-Wei Lin, Liang-Cheng Su
  • Semiconductor structure and manufacturing method thereof
    Patent number: 11756934
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure may include a logic device disposed, at a first side of the logic device, on a carrier wafer of the semiconductor structure. The semiconductor structure may include a dielectric structure disposed on a second side of the logic device, the second side being opposite the first side. The semiconductor structure may include a memory device formed on the dielectric structure.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Liang Cheng
  • Method and system for trending media programs for a user
    Patent number: 11743546
    Abstract: A client determines that a user is attempting to access media program recommendations. In response to the determination, the client attempts to collect media program recommendations to be presented to the user. Media program recommendations may be derived locally by the client, by the client and a multimedia device locally connected with the client, by the client and one or more additional devices, etc. In some embodiments, in response to receiving a query from the client, one or more recipient devices or servers identify media program recommendations in a plurality of trending categories. The media program recommendations may be selected based at least in part on EPG data and audience research and measurement data. The media program recommendations collected by the client are presented to the user for further exploration. The client may be one of mobile phones, tablet computers, etc.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 29, 2023
    Assignee: TiVo Solutions Inc.
    Inventors: Mark Berner, Gabriel Dalbec, James Yee Liang Cheng, Brian W. Beach
  • RRAM DEVICE STRUCTURE AND MANUFACTURING METHOD
    Publication number: 20230270022
    Abstract: A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventor: Chung-Liang CHENG
  • SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING
    Publication number: 20230268227
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 24, 2023
    Inventors: Yu-Ting TSAI, Chung-Liang Cheng, Ching-Jing Wu, Chyi-Tsong Ni
  • DUAL METAL CAPPED VIA CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES
    Publication number: 20230261070
    Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang CHENG, Ziwei Fang
  • Contact structure
    Patent number: 11728170
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Semiconductor device with metal gate fill structure
    Patent number: 11728171
    Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process. The process system then uses the selected process conditions data for the next etching process.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Gate capping structures in semiconductor devices
    Patent number: 11728413
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Battery pack
    Patent number: 11724606
    Abstract: The present disclosure provides a battery pack for a hybrid vehicle. The battery pack includes: multiple battery cells, a housing, a first end plate, a second end plate, a bearing plate and an upper cover, wherein the housing is provided with a bottom portion and side walls extending from the periphery of the bottom portion and forming an upper portion opening; the housing is configured for accommodating the multiple battery cells and the two end plates, when the multiple battery cells are sequentially arranged and mounted into the housing, the first end plate and the second end plate are located at two end sides of the sequentially arranged multiple battery cells to laterally fix the multiple battery cells; the bearing plate is mounted above the top portions of the multiple battery cells; and the upper cover is mounted above the housing to cover the upper portion opening of the housing.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: August 15, 2023
    Assignees: CPS Technology Holdings LLC, Clarios Advanced Solutions GmbH
    Inventors: Binbin Fan, Liang Cheng, Wei Qu, Peng Song, Yingyao Fu, Chang Liu, Jason D. Fuhr, Martin Wiegmann, Xugang Zhang, Jennifer L. Czarnecki
  • Capacitor, memory device, and method
    Patent number: 11729967
    Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Metal Loss Prevention In Conductive Structures
    Publication number: 20230253314
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Yu CHEN, Chung-Liang CHENG
  • INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20230253309
    Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 10, 2023
    Inventors: Chung-Liang CHENG, Shih Wei BIH, Yen-Yu CHEN
  • SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20230246080
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Wen TSAU, Chun-I WU, Ziwei FANG, Huang-Lin CHAO, I-Ming CHANG, Chung-Liang CHENG, Chih-Cheng LIN
  • MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF
    Publication number: 20230238324
    Abstract: A semiconductor device includes a first transistor formed on a first side of a substrate. The semiconductor device includes a first power rail structure vertically disposed over the first transistor, a second power rail structure vertically disposed over the first power rail structure, and a memory portion vertically disposed over the second power rail structure. The first power rail structure, and a second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chung-Liang Cheng
  • Semiconductor device including interface layer and method of fabricating thereof
    Patent number: 11710779
    Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, I-Ming Chang, Hsiang-Pi Chang, Yu-Wei Lu, Ziwei Fang, Huang-Lin Chao