Abstract: A pulmonary function identifying method includes: obtaining a first image, having first image elements, and a second image, having second image elements, respectively corresponding to a first state and a second state of a lung; extracting first feature points of the first image and second feature points of the second image; registering the first image with the second image using a boundary point set registeration method and an inner tissue registeration method according to the first feature points and the second feature points, so that the first image elements correspond to the second image elements and tissue units of the lung; and determining functional index values representative of the tissue units of the lung using a ventilation function quantification method according to the first image elements and the second image elements corresponding to the first image elements.

Abstract: An integrated circuit includes a first chip bonded to a second chip. The first chip includes an array of memory cells. Each memory cell includes a transistor and phase change memory element. The transistor is between the phase change memory element and the second chip.

Abstract: A resistive random access memory array includes a plurality of memory cells. Each memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element. The resistive random access memory array is used to generate physical unclonable function data.

Abstract: A method of fabricating a semiconductor structure and the semiconductor structure are disclosed. The method uses high flow rate of an etchant and an optimized scan pattern, so that the obtained semiconductor structure is a device upside-down bonded to the carrier wafer without any silicon remaining and is ready for subsequent lithography process for back via contact.

Abstract: A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.

Abstract: The present disclosure relates to the field of materials, and in particular, to a method for preparing anti-coking Ni-YSZ anode materials for SOFC. The present disclosure provides a method for preparing a SOFC anode material, including: (1) providing the mixed powder of NiO and YSZ; (2) subjecting the mixed powder provided in step (1) to two-phase mutual solid solution treatment; (3) adjusting the particle size of the product obtained in the solid solution treatment in step (2). The SOFC anode material provided by the present disclosure could prepare the SOFC anode with good carbon deposition resistance. The anode material as a whole has the advantages of low cost, good catalytic performance, desirable electronic conductivity and well chemical compatibility with YSZ, etc. The long-term stability of cell performance is strong, and the cell preparation method is also easy to achieve industrialization.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: A semiconductor device is provided. The device comprises first semiconductor wafer comprising first BEOL structure disposed on first side of first substrate, the first BEOL structure comprising first metallization layer disposed over the first substrate, second metallization layer disposed over the first metallization layer, first storage device disposed between the first and second metallization layers, and first transistor contacting the first storage device, and a first bonding layer disposed over the first BEOL structure.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an epitaxial structure over a semiconductor substrate. The semiconductor structure also includes a conductive feature over the semiconductor substrate. The conductive feature includes a high-k dielectric layer and a metal layer on the high-k dielectric layer, and a top surface of the metal layer is below a top surface of the high-k dielectric layer. The semiconductor structure further includes a metal-semiconductor compound layer formed on the epitaxial structure. In addition, the semiconductor structure includes a first metal contact structure formed on the top surface of the metal layer of the conductive feature. The semiconductor structure further includes a second metal contact structure formed on the metal-semiconductor compound layer.

Abstract: A surge protection system is provided. The surge protection system includes an input capacitor, a surge protection circuit, and a controller. When the input voltage starts to be transmitted to the input capacitor, a surge current is generated. The surge protection circuit includes a first path and a second path. The surge protection circuit is coupled to a second end of the input capacitor via the first path, so that the surge current is transmitted via the first path. The controller is coupled to the surge protection circuit. The controller is configured to provide a control signal to the surge protection circuit to switch the first path to the second path to be coupled to the second end of the input capacitor.

Abstract: A strain-relaxed silicon/silicon germanium (Si/SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.

Abstract: A thermal insulation backpack enabling a rapid reduction in temperature without removing a product arranged therein and achieving a thermal insulation effect, and an operation method thereof. The thermal insulation backpack comprises a main body (10) and one or more adapter assembly (30). The main body (10) is provided with a thermal insulation accommodation cavity (102) therein, and provided with a connection hole (101) in communication with the thermal insulation accommodation cavity (102). The adapter assembly (30) is inserted into the connection hole (101), and comprises a fixing frame, a sealing screen (32), and a reset assembly. An outer periphery of the sealing screen (32) is provided with a sealing strip (321) protruding outward. A connection recess (316) and a first through slot (312) are provided in the fixing frame. The first through slot (312) is connected to the thermal insulation accommodation cavity (102). The sealing screen (32) is connected to the reset assembly.

Abstract: In fabrication of a phase change random access memory (PCRAM), a field effect transistor (FET) logic layer is formed on a first wafer, including a heating FET for each storage cell. The FET logic layer is transferred from the first wafer to a carrier wafer. Thereafter, a storage layer of the PCRAM is formed on the exposed surface of the FET logic layer, including a region of a phase change material for each storage cell that is electrically connected to a channel of the heating FET of the storage cell. The storage layer further includes a second heating transistor for each storage cell that is electrically connected to a channel of the second heating transistor.

Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures stacked over a substrate and spaced apart from one another, gate dielectric layers wrapping around the nanostructures respectively, nitride layers wrapping around the gate dielectric layers respectively, oxide layers wrapping around the nitride layers respectively, work function layers wrapping around the oxide layers respectively, and a metal fill layer continuously surrounding the work function layers.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed, The method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. The first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions, The second oxygen diffusivity is higher than the first oxygen diffusivity. The fourth thickness is greater than the third thickness.

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: Image sensing devices according to present disclosure include metal gate structures in a pixel device. Particularly, the metal gate structures include a ferroelectric layer and a conductive layer to form a negative capacitance device in the gate stack. As a result, the transistors in the pixel device have reduced threshold swing, improved gain and reduced threshold voltage shift. The pixel device according to the present disclosure includes a combination of metal gate and polycrystalline gate, which provides flexibility in pixel device design and improves performance.