Patents by Inventor Liang Han

Liang Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10419460
    Abstract: The present teaching generally relates to detecting abnormal user activity associated with an entity. In a non-limiting embodiment, baseline distribution data representing a baseline distribution characterizing normal user activities for an entity may be obtained. Information related to online user activities with respect to the entity may be received, distribution data representation a dynamic distribution may be determined based, at least in part, on the information. One or more measures characterizing a difference between the baseline distribution and the dynamic distribution may be computed, and in real-time it may be assessed whether the information indicates abnormal user activity. If the first information indicates abnormal user activity, then output data including the distribution data and the one or more measures may be generated.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: September 17, 2019
    Assignee: Oath, Inc.
    Inventors: Liang Wang, Angus Xianen Qiu, Chun Han, Liang Peng
  • Patent number: 10393540
    Abstract: Technologies for determining a user's location include a mobile computing device (100) to determine, based on sensed inertial characteristics of the device, a walking gait of a user. The walking gait is one of a first gait indicative of the user holding the device to the user's side or a second gait indicative of the user swinging the device along the user's side. The device further detects that the user has taken a physical step based on the inertial characteristics and the determined walking gait of the user, and determines a raw directional heading of the device indicative of a direction of the physical step. The device determines an estimated location of the user based on the determined raw directional heading, an estimated step length, and the user's previous location.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Ke Han, Xun Wang, Xiaodong Cai, Liang Li
  • Publication number: 20190252277
    Abstract: A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Shin HAN, Yen-Miao LIN, Chung-Chih CHEN, Hsien-Liang MENG
  • Patent number: 10381715
    Abstract: An electronic device may include an antenna having a resonating element, an antenna ground, and a feed. First and second tunable components may be coupled to the resonating element. Adjustable matching circuitry may be coupled to the feed. Control circuitry may use the first tunable component to tune a midband antenna resonance when sensor circuitry identifies that the device is being held in a right hand and may use the second tunable component to tune the midband resonance when the sensor circuitry identifies that the device is being held in a left hand. For tuning a low band resonance, the control circuitry may place the antenna in different tuning states by sequentially adjusting a selected one of the matching circuitry and the tunable components, potentially reverting to a previous tuning state at each step in the sequence. This may ensure that antenna efficiency is satisfactory regardless of antenna loading conditions.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 13, 2019
    Assignee: Apple Inc.
    Inventors: Liang Han, Thomas E. Biedka, Matthew A. Mow, Iyappan Ramachandran, Mattia Pascolini, Xu Han, Hao Xu, Jennifer M. Edwards, Salih Yarga, Yijun Zhou
  • Publication number: 20190241376
    Abstract: The disclosed system for loading and unloading the substrate includes: a substrate rotation apparatus having a first rotation position and a second rotation position with a difference in rotation angle of 90 degrees, wherein the substrate rotation apparatus includes two layers of sucker assemblies, each of which includes a plate body, a plurality of support suction tubes arranged on the plate body, and first suckers connected with tops of respective support suction tubes respectively, and there are gaps, for inserting the substrate therein, between respective first suckers of a lower layer of sucker assembly, and a plate body of an upper layer of sucker assembly; and a mechanical hand including a plurality of mechanical fingers capable of holding two halves of the substrate, both of which are arranged in a length direction of the mechanical fingers, and joined together into an entire substrate.
    Type: Application
    Filed: October 10, 2017
    Publication date: August 8, 2019
    Inventors: Jianlin FENG, Dawei HAN, Jianjun LIN, Liang ZHOU
  • Patent number: 10372000
    Abstract: There is disclosed a method of manufacturing an array substrate, the method including a step of forming thin film transistors on a substrate; wherein the step of forming the thin film transistors on the substrate includes: forming a first electrically conductive layer on the substrate; forming an insulating layer on the first electrically conductive layer; forming at least one common holes in the insulating layer to communicate with the first electrically conductive layer; forming a first connection portion, which is made of the same material as a second electrically conductive layer, in the at least one of the at least one common holes while forming the second electrically conductive layer on the insulating layer by using a single process, the first connection portion being in electrical contact with the first electrically conductive layer. In addition, there is disclosed an array substrate manufactured by the above method and a display device including the array substrate.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 6, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Botao Song, Liang Lin, Tao Ma, Wenlong Wang, Ling Han, Yu Wei
  • Publication number: 20190227222
    Abstract: A light guide assembly comprises: a first light guide member; and a second light guide member stacked on the first light guide member. The light guide assembly has first and second light incident surfaces located on different sides, and a light emitting surface and a bottom surface which are oppositely disposed in a thickness direction, the first light incident surface and the bottom surface are located on the first light guide member, and the second light incident surface and the light emitting surface are located on the second light guide member, and the bottom surface is provided with first dots having a density increasing in a direction away from the first light incident surface, and the light emitting surface is provided with second dots having a density increasing in a direction away from the second light incident surface.
    Type: Application
    Filed: August 16, 2018
    Publication date: July 25, 2019
    Inventors: Heling ZHU, Junjie MA, Yuanda LU, Bo HAN, Liang GAO, Lu YU, Pengfei CHENG
  • Patent number: 10358728
    Abstract: An electrode material for a direct fuel cell or an electrochemical hydrogenation electrolytic tank, includes component A, or component B, or the mixture of component A and component B. The component A is any one of or a mixture of two or more than two of HnNb2O5, HnV2O5, HnMoO3, HnTa2O5 or HnWO3 at any ratio, where 0<n?4. The component B is any one of or a mixture of two or more than two of Nb2O5, V2O5, MoO3, Ta2O5, WO3 at any ratio.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 23, 2019
    Assignee: WUHAN HYNERTECH CO., LTD.
    Inventors: Hansong Cheng, Chaoqun Han, Ming Yang, Gang Ni, Liang Huang, Libin Pei
  • Patent number: 10354072
    Abstract: A system configured to detect malware is described. The system configured to detect malware including a data collector configured to detect at least a first hypertext transfer object in a chain of a plurality of hypertext transfer objects. The data collector further configured to analyze at least the first hypertext transfer object for one or more events. And, the data collector configured to generate a list of events based on the analysis of at least the first hypertext transfer object.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: July 16, 2019
    Assignee: Cyphort Inc.
    Inventors: Alexander Burt, Mikola Bilogorskiy, McEnroe Navaraj, Frank Jas, Liang Han, Yucheng Ting, Manikandan Kenyan, Fengmin Gong, Ali Golshan, Shishir Singh
  • Patent number: 10356941
    Abstract: An air-cooling heat dissipation device includes a base, a swirling-airflow heatsink, an air pump and a passage connector. The base is located beside an electronic component while the air pump is fixed on the base. The swirling-airflow heatsink is attached on the electronic component and includes a swirling passage defined by a conductive line and a thermal conduction plate collaboratively. An airflow-guiding chamber is defined by the air pump and the base collaboratively, and the airflow-guiding chamber is in communication with the swirling passage by the passage connector. When the air pump is enabled, an ambient air is introduced into the airflow-guiding chamber of the base and transferred to the swirling passage of the swirling-airflow heatsink through a discharge opening of the base and the passage connector. Consequently, a fast swirling air flow is produced to cool the electronic component.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 16, 2019
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Zhen-Chun Xu, Kuei-Liang Chiang, Yung-Kang Lin, Chi-Feng Huang, Yung-Lung Han
  • Patent number: 10347184
    Abstract: A pixel compensation circuit, a driving method and a display device are disclosed. The pixel compensation circuit includes: a light-emitting element; a driving switch, a first terminal is connected to a power source voltage; a first switch and a control terminal is connected to a first scanning signal, a first terminal is connected to a data signal; a second switch, a control terminal is connected to a control signal and a first terminal is connected to the second terminal of the driving switch; a third switch, a control terminal is connected to a second scanning signal; a storage capacitor, a first terminal is connected to a control terminal of the driving switch, a second terminal is connected to the second terminal of the second switch. Through the above method, the affection of the current flowing through the light-emitting element caused by the threshold voltage of the driving switch is canceled.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Baixiang Han, Liang Sun
  • Patent number: 10345867
    Abstract: A shaft structure includes a rotation shaft, a transmission structure coupled to the rotation shaft, and a moving structure coupled to the transmission structure. The rotation shaft includes a first transmission member fixedly arranged on the rotation shaft. The transmission structure rotates along with the rotation shaft, and includes a second transmission member engaged with the first transmission member. The moving structure moves translationally with respect to the rotation shaft in response to a rotation of the transmission structure.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 9, 2019
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventors: Tianshui Tan, Liang Han, Ran Zhang
  • Publication number: 20190205393
    Abstract: A cross-media search method using a VGG convolutional neural network (VGG net) to extract image features. The 4096-dimensional feature of a seventh fully-connected layer (fc7) in the VGG net, after processing by a ReLU activation function, serves as image features. A Fisher Vector based on Word2vec is utilized to extract text features. Semantic matching is performed on heterogeneous images and the text features by means of logistic regression. A correlation between the two heterogeneous features, which are images and text, is found by means of semantic matching based on logistic regression, and thus cross-media search is achieved. The feature extraction method can effectively indicate deep semantics of image and text, improve cross-media search accuracy, and thus greatly improve the cross-media search effect.
    Type: Application
    Filed: December 1, 2016
    Publication date: July 4, 2019
    Applicant: Peking University Shenzhen Graduate School
    Inventors: Wenmin Wang, Liang Han, Mengdi Fan, Ronggang Wang, Ge Li, Shengfu Dong, Zhenyu Wang, Ying Li, Hui Zhao, Wen Gao
  • Publication number: 20190196788
    Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.
    Type: Application
    Filed: August 3, 2018
    Publication date: June 27, 2019
    Inventors: Liang HAN, Xiaowei JIANG
  • Publication number: 20190196814
    Abstract: The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 27, 2019
    Inventors: Liang HAN, Xiaowei JIANG
  • Publication number: 20190196970
    Abstract: The present disclosure relates to a unified memory apparatus having a unified storage medium and one or more processing units. The unified memory apparatus can include a first storage module having a first plurality of storage cells, and a second storage module having a second plurality of storage cells, each of the first and second plurality of storage cells configured to store data and to be identified by a unique cell identifier. The one or more processing units are in communication with the unified storage medium and the processing units are configured to receive a first input data from one of the first plurality of storage cells, receive a second input data from one of the second plurality of storage cells, and generate an output data based on the first and second input data.
    Type: Application
    Filed: May 18, 2018
    Publication date: June 27, 2019
    Inventors: Liang HAN, Xiaowei JIANG, Jian CHEN
  • Publication number: 20190197001
    Abstract: The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.
    Type: Application
    Filed: November 27, 2018
    Publication date: June 27, 2019
    Inventors: Liang HAN, Xiaowei JIANG, Jian CHEN
  • Publication number: 20190196831
    Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Liang HAN, Xiaowei JIANG, Jian CHEN
  • Publication number: 20190196840
    Abstract: The present disclosure provides systems and methods for executing instructions. The system can include: processing unit having a core configured to execute instructions; and a host unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein the set of instructions each includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions, and provide the set of instructions to the core.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Liang HAN, Xiaowei JIANG
  • Patent number: 10325810
    Abstract: A memory and a method for fabricating the memory are provided. The method includes forming a plurality of first gate structures on a base substrate. Each first gate structure includes a floating gate structure and a control gate structure. The control gate structure includes a body region and a top region. A size of the top region is smaller than a size of the body region along a direction perpendicular to a length direction of the control gate structure. A sidewall of the top region is connected to a sidewall of the body region. The method also includes forming a dielectric layer on the base substrate and covering the plurality of first gate structures, while simultaneously forming air gaps in the dielectric layer between the adjacent first gate structures. A top of each air gap is above or coplanar with a top surface of the control gate structure.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: June 18, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Liang Han, Sheng Fen Chiu, Liang Chen