Abstract: Virtualization techniques can include determining virtual function routing tables for the virtual parallel processing units (PPUs) from a logical topology of a virtual function. A first mapping of the virtual PPUs to a first set of a plurality of physical PPUs can be generated. Virtualization can also include generating a first set of physical function routing tables for the first set of physical PPUs based on the virtual function tables and the first virtual PPU to physical PPU mapping. An application can be migrated from the first set of physical PPUs to a second set of PPUs by generating a second mapping of the virtual PPUs to a second set of a plurality of physical PPUs. A second set of physical function routing table for the second set of physical PPUs can also be generated based on the virtual function tables and the second virtual PPU to physical PPU mapping.

Abstract: A connection mechanism includes a first connection unit, a second connection unit, and a separation and locking control structure. The second connection unit is separated from and locked with the first connection unit in an insertion method. The separation and locking control structure includes a first control member and a second control member. The first control member is connected to the first connection unit to drive the first connection unit to move between a first position and a second position. The second control member abuts against the second connection unit when the second connection unit is inserted into the first connection unit. The first control member and the second control member have a first status and a second status.

Abstract: An electronic apparatus includes a first body, a second body, and a flexible screen. The second body is rotatably connected to the first body through a rotation shaft device to cause an opening and closing angle of the first body relative to the second body to be adjustable. The flexible screen is configured to display images. An end of the flexible screen is slidably arranged at the first body along a connection line direction of the first body and the second body. A second end is slidably arranged at the second body along the line connection direction. The first end and the second end are two ends of the flexible screen in the connection line direction. The first end and the second end of the flexible screen synchronously slide along the connection line direction to adjust a size of a part of the flexible screen located at the first body.

Abstract: A method for operating an electronic device to browse a collection of images. The method includes performing by a processing unit of the device: determining a target person, the target person being a person involved in an operation performed using the an electronic device; adapting a subset of the collection of images based on people represented in the images as a function of the target person, wherein the adapting includes selecting and/or sorting the subset of the collection of images; and displaying, on an interface of the device the subset of the collection of images, the displayed subset of images being arranged according to the adapting.

Abstract: A disclosed computer-implemented method may include receiving, from a sensor included in an artificial reality system, data representative of an environment local to the artificial reality system. The disclosed method may also include determining, based on the received data representative of the environment, a probability that an environmental condition will impact a use of a plurality of antennas included in the artificial reality system by the artificial reality system. The disclosed method may also include adjusting, in response to the determined probability that the environmental condition will interfere with the use of the plurality of antennas, the use of the plurality of antennas by the artificial reality system. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems and methods for heterogenous hardware acceleration are disclosed. The systems and methods can include a neural network processing unit comprising compute tiles. Each of a first set of the compute tiles can include a first tensor array configured to support operations in a first number format. Each of a second set of the compute tiles can include a second tensor array configured to support operations in a second number format, the second number format supporting a greater range or a greater precision than the first number format, and a de-quantizer configured to convert data in the first number format to data in the second number format. The systems and methods can include neural network processing units, multi-chip hardware accelerators and distributed hardware accelerators including low-precision components for performing interference tasks and high-precision components for performing training tasks.

Abstract: A method for operating an electronic device to browse a collection of images. The method includes: sorting a subset of the collection of images based on a sorting of people represented in the images; and displaying, on an interface of the electronic device, the subset of the collection of images, the displayed subset of images being arranged according to the sorting.

Abstract: The disclosed system may include a main logic board (MLB) that includes a ground plane, an antenna feed that is electrically connected to the MLB, an antenna arm electrically connected to the antenna feed, and a slot antenna formed into at least part of the MLB. The slot antenna may be electrically connected to the antenna feed. Various other apparatuses and mobile electronic devices are also disclosed.

Abstract: The disclosed system may include a frame, a printed circuit board (PCB) mounted to the frame, and at least one antenna electrically connected to the PCB via an antenna feed. The antenna may be shorter than a maximum specified length, and the antenna may be intended to operate within a specified frequency range for which the antenna's length is insufficiently long. Still further, in this system, electrical current flowing to the antenna may be routed to at least a portion of the frame to create a parasitic arm. As such, the parasitic arm may radiate in conjunction with the antenna, providing constructive interference in the specified frequency range. Various other mobile electronic devices, apparatuses, and methods of manufacturing are also disclosed.

Abstract: A system includes a high-bandwidth inter-chip network (ICN) that allows communication between parallel processing units (PPUs) in the system. For example, the ICN allows a PPU to communicate with other PPUs on the same compute node or server and also with PPUs on other compute nodes or servers. In embodiments, communication may be at the command level (e.g., at the direct memory access level) and at the instruction level (e.g., the finer-grained load/store instruction level). The ICN allows PPUs in the system to communicate without using a PCIe bus, thereby avoiding its bandwidth limitations and relative lack of speed. The respective routing tables comprise information of multiple paths to any given other PPU.

Abstract: A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Abstract: The disclosed system may include a support structure having a top portion and a first bottom portion. The system may also include at least one wireless communication device positioned on the top portion of the support structure. The system may further include at least one antenna positioned in the first bottom portion of the support structure. The antenna in the first bottom portion of the support structure may be electrically connected to the wireless communication device positioned on the top portion of the support structure. Various other wearable devices, apparatuses, and methods of manufacturing are also disclosed.

Abstract: The disclosed system may include a support structure that may be configured to house electronic components. The system may also include a first antenna mounted to the support structure. The first antenna may be configured to provide a wireless intralink on a first frequency to a local mobile electronic device. The system may also include multiple second antennas that are configured to established wireless interlinks on other frequencies to various external wireless networks. The second antennas may be positioned a specified minimum distance away from the first antenna and may be positioned at an at least partially opposing angle to each other. As such, the second antennas may provide at least a minimum threshold amount of spherical radiation to transmit and receive data using the established wireless interlinks. Various other apparatuses, methods of manufacturing, and mobile electronic devices are also disclosed.

Abstract: Embodiments of the present disclosure present a hyper-square interconnect topology and advanced ring-based AllReduce operations. In some embodiments, a topology is provided that is an improvement over conventional interconnect topologies by eliminating delays associated with long wirings. In some embodiments, computing nodes are divided into sub-sections to better allocate computing tasks, and the system can be optimized to divide up the computing nodes by maximizing the number of square sub-sections in the topology. In some embodiments, the system can be optimized to select square sub-sections first for each computing task. Each sub-section can comprise some computing nodes or all computing nodes in the hyper-square interconnect topology. This flexibility allows the hyper-square interconnect topology to utilize the computing nodes more efficiently by assigning appropriate numbers of computing nodes to each computing task based on the computing need of the computing task.

Abstract: The disclosed system may include an antenna and an antenna matching network. The antenna matching network may include an aperture tuner configured to shift a frequency response of the antenna and an impedance tuner configured to dynamically change an amount of radiated power for the antenna. The antenna matching network may be positioned at least a specified minimum distance from the antenna according to various operating characteristics of the antenna. Various other apparatuses, wearable electronic devices, and methods of manufacturing are also disclosed.

Abstract: The disclosed system may include a support structure, a lens mounted to the support structure, where the lens includes at least one conductive layer that includes conductive material, and an antenna disposed on the support structure within a specified maximum distance from the lens. Various characteristics of the lens or the antenna may be modified to reduce coupling between the antenna and the layer of conductive material in the lens. Various other wearable devices, apparatuses, and methods of manufacturing are also disclosed.

Abstract: A method for manufacturing a flash memory device is provided. The method includes: providing a substrate structure including a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, and a gap structure between the gate structures; forming an overhang surrounding an upper portion of the gate structures to form a gap structure between the gate structures; and forming a second isolation region filling an upper portion of the gap structures and leaving a first air gap between the gap structures.

Abstract: Improved convolutional layers for neural networks can obtain an input feature map comprising groups of channels. Each group of channels can include one or more channels having a predetermined size. The predetermined sizes can differ between the groups. The convolutional layer can generate, for each one of the groups of channels, an output channel. Generation of the output channel can include resizing the channels in the remaining groups of channels to match the predetermined size of the each one of the groups of channels. Generation can further include combining the channels in the each one of the groups with the resized channels and applying the combined channels to a convolutional sub-layer to generate the output channel.

Abstract: A system includes a high-bandwidth inter-chip network (ICN) that allows communication between parallel processing units (PPUs) in the system. For example, the ICN allows a PPU to communicate with other PPUs on the same compute node or server and also with PPUs on other compute nodes or servers. In embodiments, communication may be at the command level (e.g., at the direct memory access level) and at the instruction level (e.g., the finer-grained load/store instruction level). The ICN allows PPUs in the system to communicate without using a PCIe bus, thereby avoiding its bandwidth limitations and relative lack of speed. The respective routing tables comprise information of multiple paths to any given other PPU.

Abstract: Systems and methods for exchanging synchronization information between processing units using a synchronization network are disclosed. The disclosed systems and methods include a device including a host and associated neural processing units. Each of the neural processing units can include a command communication module and a synchronization communication module. The command communication module can include circuitry for communicating with the host device over a host network. The synchronization communication module can include circuitry enabling communication between neural processing units over a synchronization network. The neural processing units can be configured to each obtain a synchronized update for a machine learning model. This synchronized update can be obtained at least in part by exchanging synchronization information using the synchronization network. The neural processing units can each maintain a version of the machine learning model and can synchronize it using the synchronized update.