Patents by Inventor Liang Huang

Liang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147600
    Abstract: A new ring coupling structure for a linear accelerator includes an acceleration cavity, a coupling cavity, and a beam hole. The acceleration cavity and the coupling cavity are alternately assembled together. The beam hole penetrates through the acceleration cavity and the coupling cavity. The acceleration cavity adopts a bowl-shaped structure, a convex cone structure with a mesoporous is disposed on an inner wall of the acceleration cavity along the beam hole. Coupling holes between the acceleration cavity and the coupling cavity are designed as at least two waist-shaped holes uniformly distributed around the beam hole. The coupling cavity adopts a disc-shaped cavity structure with a thickened edge, and a nose cone is disposed in the coupling cavity and welded with cavity walls at both ends of a coupler. The left and right waveguide plates of the coupling cavity are welded together by using the nose cone.
    Type: Application
    Filed: February 28, 2023
    Publication date: May 2, 2024
    Applicant: CHENGDU ELEKOM VACUUM ELECTRON TECHNOLOGY CO. LTD
    Inventors: Lin ZHOU, Hao TAO, Jin GUO, Hong HUANG, Liang HU, Mi TANG
  • Publication number: 20240145691
    Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.
    Type: Application
    Filed: March 14, 2023
    Publication date: May 2, 2024
    Inventors: CHUAN-PU LIU, YIN-WEI CHENG, SHIH-AN WANG, BO-LIANG PENG, CHUN-HUNG CHEN, JUN-HAN HUANG, YI-CHANG LI
  • Publication number: 20240146097
    Abstract: A vehicle power management system and an operating method thereof are provided. The vehicle power management system is adapted for a vehicle load device and a vehicle power supply, and includes a control circuit, a charge/discharge circuit and a backup battery. The control circuit is electrically connected to the vehicle power supply and the vehicle load device, and monitors an output voltage of the vehicle power supply and determines according to the output voltage whether a vehicle engine is started. The charge/discharge circuit is electrically connected to the control circuit and the backup battery. When the vehicle engine is started, the charge/discharge circuit supplies power of the vehicle power supply to the backup battery and the vehicle load device. When the vehicle engine is not started, the backup battery discharges the charge/discharge circuit and the charge/discharge circuit supplies power of the backup battery to the vehicle load device.
    Type: Application
    Filed: March 8, 2023
    Publication date: May 2, 2024
    Inventors: YUNG-LE HUNG, CHENG-LIANG HUANG
  • Publication number: 20240141205
    Abstract: This disclosure relates to a composition that includes at least one first ruthenium removal rate enhancer; at least one copper removal rate inhibitor; at least one low-k removal rate inhibitor; and an aqueous solvent.
    Type: Application
    Filed: January 10, 2024
    Publication date: May 2, 2024
    Inventors: Ting-Kai Huang, Bin Hu, Yannan Liang, Hong Piao
  • Publication number: 20240145342
    Abstract: In an embodiment, a package includes an encapsulant laterally surrounding a first integrated circuit device and a second integrated circuit device, wherein the first integrated circuit device includes a die and a heat dissipation structure over the die; a sealant disposed over the heat dissipation structure; an adhesive disposed over the second integrated circuit device; and a lid disposed over the sealant and the adhesive, wherein the lid includes a first cooling passage and a second cooling passage, the first cooling passage including an opening at a bottom of the lid and aligned to the heat dissipation structure, the second cooling passage including channels aligned to the second integrated circuit device and being distant from the bottom of the lid.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 2, 2024
    Inventors: Tung-Liang Shao, You-Rong Shaw, Yu-Sheng Huang, Chen-Hua Yu
  • Patent number: 11972984
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: April 30, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 11971822
    Abstract: Techniques are disclosed relating to filtering messages. A computer system may detect an occurrence of an event of a particular type. The computer system may determine whether to enqueue, in a message queue, a message that identifies a set of tasks to be performed in relation to the event. The determination may be based on a response received from a cache that stores a subset of filter rules of a filter rules table. Based on the response indicating a cache miss, the computer system may enqueue the message in the message queue. A process that processes the message may be operable to resolve the cache miss by 1) accessing a filter rule from the filter rules table that indicates whether messages for events of the particular type should be enqueued in the message queue and 2) updating the cache to store the filter rule.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 30, 2024
    Assignee: Salesforce, Inc.
    Inventors: Liang Xie, Igor Shmulevich, Ritesh Vaja, Zhijian Huang, Bowen Wang
  • Publication number: 20240136516
    Abstract: Disclosed are a cathode active material for sodium-ion batteries and a preparation method therefor and an application thereof. The cathode active material has a chemical formula of NaxNiyFezMngMhAmO2, where M is selected from the group consisting of Ti, Al, Mg, Ca, Zr, Y, Zn, Nb, W and combinations thereof, A is selected from the group consisting of B, P, C and combinations thereof, 0.80?x?1.40, 0.05?y?0.95, 0.05?z?0.95, 0.05?g?0.95, 0.01?h?0.50, and 0.01?m?0.30. By adding M and A elements to the ternary iron-manganese-nickel cathode active material for sodium-ion batteries, and controlling the ratio of all elements, the present disclosure can achieve the formation of a perfect layered single-crystal structure of the cathode active material for sodium-ion batteries, with large particles, ultimately achieving the stability of the active material, and when used in sodium-ion batteries, it can significantly improve the cycling performance at high temperatures while ensuring high gram capacity.
    Type: Application
    Filed: March 22, 2022
    Publication date: April 25, 2024
    Inventors: Liming GONG, Huan ZHONG, Jie HUANG, Wen JIANG, Liang CHEN
  • Publication number: 20240130762
    Abstract: An artificial bone plate unit and an assembleable artificial bone plate are provided. The artificial bone plate unit includes a plate body, multiple connecting pins, connecting holes, drug cavities, and drug-releasing openings. The plate body has two main surfaces and a peripheral surface connected between the two main surfaces. The connecting pins and the connecting holes are formed on the plate body and arranged along the peripheral surface on the plate body. The connecting holes correspond in shape to the connecting pins. The drug cavities are formed in the artificial bone plate unit and are connected to the drug-releasing openings. The artificial bone plate units are connected using the connecting pins and the connecting holes to form the assembleable artificial bone plate. The assembleable artificial bone plate can be bent into the shape of a defect area of the skull, which saves material and time.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: Tung-Kuo TSAI, Keng-Liang OU, Yung-Kang SHEN, Yin-Chung HUANG, Kuo-Sheng HUNG, Yu-Sin OU
  • Publication number: 20240130276
    Abstract: A riding mowing device includes a seat used for a user to sit on and including a seat cushion and a backrest; a frame for supporting the seat; a cutting assembly including a cutting deck and a mowing element for mowing grass, where the mowing element is at least partially accommodated in the cutting deck, and the cutting assembly is mounted to the frame; a traveling assembly for driving the riding mowing device to travel; a control circuit board for controlling at least the cutting assembly and the traveling assembly; and a power supply assembly for supplying power to at least the cutting assembly and the traveling assembly. At least part of the control circuit board is disposed between the seat and the power supply assembly.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 25, 2024
    Inventors: Li Li, Tianfang Wei, Fan Gao, Liang Chen, Haishen XU, Ming Gao, Min Zhang, Tao Zhang, Jiajun Huang, Yunfei Gao
  • Publication number: 20240136423
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11965647
    Abstract: The present disclosure provides an LED plant growing lamp including a power supply, a plurality of LED modules, and a frame including four connecting rods and two end caps; each LED module including a heat sink, an LED light board and a junction box installed on the heat sink; each two of the four connecting rods arranged opposite each other and connected through a corresponding end cap to form a rectangular frame, the two end caps respectively arranged at both ends of the connecting rod; the power supply electrically connected with the junction box, the junction box electrically connected with the LED light board; the plurality of LED modules arranged in a row and sequentially installed on the four connecting rods, and received in the rectangular frame, thereby adjusting different luminous quantities and reducing R&D costs without needing to set heat sinks with different structures according to different luminous quantities.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: April 23, 2024
    Assignee: SHENZHEN SNC OPTO ELECTRONIC CO., LTD
    Inventors: Jianjun Xu, Liang Qiu, Xican Huang, Jianyong Xu
  • Patent number: 11967575
    Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 23, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Javier A. DeLaCruz, Shaowu Huang, Liang Wang, Gaius Gillman Fountain, Jr., Rajesh Katkar, Cyprian Emeka Uzoh
  • Publication number: 20240124350
    Abstract: A quantum dot composite structure and a method for forming the same are provided. The quantum dot composite structure includes: a glass particle including a glass matrix and a plurality of quantum dots located in the glass matrix, wherein at least one of the plurality of quantum dots includes an exposed surface in the glass matrix; and an inorganic protective layer disposed on the glass particle and covering the exposed surface.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 18, 2024
    Inventors: Ching LIU, Wen-Tse HUANG, Ru-Shi LIU, Pei Cong YAN, Chai-Chun HSIEH, Hung-Chun TONG, Yu-Chun LEE, Tzong-Liang TSAI
  • Publication number: 20240128353
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20240127783
    Abstract: Provided are a noise cancellation method and apparatus, an electronic device, a noise cancellation earphone, and a storage medium. The method includes acquiring original sound source information; performing noise reduction (NR) processing on the original sound source information using active noise cancellation (ANC) to obtain first sound information and performing the NR processing on the original sound source information using environmental noise cancellation (ENC) to obtain second sound information; and mixing and adding the first sound information and the second sound information to obtain target sound information and playing the target sound information. In this method, the NR processing can be performed on the sound using the ANC and the ENC, thereby distinguishing environmental noise from human voice, improving the noise cancellation performance, and enabling a user to hear clearer sound.
    Type: Application
    Filed: April 3, 2023
    Publication date: April 18, 2024
    Applicant: Lanto Electronic Limited
    Inventors: Che-Yung Huang, Chi-Liang Chen, Yong-Sheng Jheng, Che-Yi HSIAO
  • Patent number: 11960253
    Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 16, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Yu Huang, Chun-Fang Chen, Hong-Chi Ku, Te-Ming Chen, Chien-Liang Lai, Sen-Chia Chang
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240118492
    Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers.
    Type: Application
    Filed: November 14, 2023
    Publication date: April 11, 2024
    Inventors: Shaowu HUANG, Javier A. DELACRUZ, Liang WANG, Guilian GAO
  • Patent number: 11955338
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen