Patents by Inventor Liang Pan

Liang Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12293910
    Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 12278277
    Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: April 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Liang Pan, Yung Tzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
  • Patent number: 12263873
    Abstract: An implementation method for an independent multimode train control system based on a trackside platform is provided. According to the implementation method, a trackside train control system and an interlocking system are provided independently to meet requirements of hybrid operation of trains having different systems; and at the same time, during operation of a train in a moving block mode, once a trackside control system fails or an on-board system fails, the multimode train control system can ensure that the train is degraded automatically and operates according to a degraded mode.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: April 1, 2025
    Assignee: CASCO SIGNAL LTD.
    Inventors: Liang Pan, Xiaoyong Wang, Yanyang Xing, Haigui Xu, Huaxiang Liu, Lingjiao Hong, Shaowen Chen
  • Patent number: 12246763
    Abstract: A disclosure relates to a degradation management method for a versatile signal system, a device and a medium. The versatile signal system supports both the CTCS system for the national railway and the CBTC system for the urban railway; the method controls the safety of trains equipped with the CTCS system or the CBTC system on the same line, and effectively conducts degraded operation management; and the management method comprises switching between normal operation modes of the CTCS system and the CBTC system, switching between degraded operation modes, and switching between normal operation modes and degraded operation modes in a shared area. Compared with the prior art, the disclosure has the advantage that effective degradation operation mode management on trains running on a line under a CTCS+CBTC signal system is realized.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: March 11, 2025
    Assignee: CASCO SIGNAL LTD.
    Inventors: Zhaoyao Wang, Xiaoyong Wang, Huaxiang Liu, Donghai Wang, Xiaoque Ling, Liang Pan
  • Publication number: 20250073989
    Abstract: A method of additive manufacturing includes directing a first photon beam onto a resin and directing a second photon beam onto the resin to generate a reactive species from the initiator molecule to thereby polymerize a portion of the resin. The resin includes an initiator molecule and a sensitizer molecule. The first photon beam simultaneously excites each of the initiator molecule and the sensitizer molecule, transitions each of the initiator molecule and the sensitizer molecule into their respective singlet excited states; and transfers, at least one of energy or electrons, from the singlet excited state of the sensitizer molecule to the initiator molecule.
    Type: Application
    Filed: August 28, 2024
    Publication date: March 6, 2025
    Inventors: Liang Pan, Xianfan Xu, Bryan W. Boudouris
  • Patent number: 12237228
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20250042454
    Abstract: The present invention relates to a intelligent management and control system for rail transit operation safety, wherein the system, together with a train control system, an operation and maintenance terminal and a passenger information system, monitors rail transit operation risks in real time, wherein the management and control system includes a main module, a terminal interface module, a security gateway, and an information release gateway; the main module is connected to the terminal interface module, the security gateway, and the information release gateway respectively; the terminal interface module is connected to the operation and maintenance terminal; the security gateway is connected to the train control system; and the information release gateway is connected to the terminal interface module and the passenger information system respectively. Compared with the prior art, the present invention has the advantages of unified platform, high efficiency and simplified management and control process.
    Type: Application
    Filed: November 30, 2022
    Publication date: February 6, 2025
    Inventors: Xiaoyong WANG, Liang PAN, Shaowen CHEN, Huaxiang LIU, Jing YUAN
  • Patent number: 12217936
    Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
  • Patent number: 12210096
    Abstract: A radar system includes an ultrasonic radar unit and a warning device. The ultrasonic radar unit is configured to be detachably mounted on a vehicle, and is configured to output a pairing signal when a pairing function is activated and output a warning signal upon detecting an object that is within a range. The warning device is configured to be electrically connected to the ultrasonic radar unit and to be mounted inside the vehicle. The warning device is configured to wirelessly communicate with the ultrasonic radar unit to receive the warning signal and the pairing signal; when receiving the pairing signal, couple the ultrasonic radar unit to one of a plurality of warning areas that is on the warning device according to the pairing signal; control one of the warning areas that is coupled to the ultrasonic radar unit to output a visual warning upon receiving the warning signal.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: January 28, 2025
    Assignee: Vision Automobile Electronics Industrial Co., Ltd.
    Inventors: Tien-Bou Wan, Chung-Hsiao Lo, Chien-Liang Pan, An-Hun Cheng, Chia-Hung Wu
  • Patent number: 12205816
    Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20240416979
    Abstract: The present invention relates to a method, device and storage medium for sequencing and managing rail transit line resources. The method includes the following steps: step S101: analyzing a trackside line loop deadlock scenario and establishing a static deadlock prevention policy; step S102: reasonably making an operation plan to avoid resource deadlock loop wait; step S103: applying for all required resources for each train at a time; step S104: establishing an operation task order verification mechanism; and step S105: monitoring and executing an operation task. Compared with the prior art, the present invention can reduce the idle time of the line resources, improve the utilization rate of the line resources, and avoid the problems of operation deadlock and the mismatch between an actual train operation task and the operation plan.
    Type: Application
    Filed: November 30, 2022
    Publication date: December 19, 2024
    Inventors: Liang PAN, Xiaoyong WANG, Shaowen CHEN, Xiaoque LING, Wei FENG, Hao GAO, Xuan ZHANG
  • Publication number: 20240395536
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chia-Yang Hung, Huan-Just Lin, Sheng-Liang Pan, Yungtzu Chen, Po-Chuan Wang, Guan-Xuan Chen
  • Patent number: 12154784
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yang Hung, Huan-Just Lin, Sheng-Liang Pan, Yungtzu Chen, Po-Chuan Wang, Guan-Xuan Chen
  • Publication number: 20240387698
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a silicon oxycarbonitride spacer, a silicon oxycarbide spacer, a silicon nitride spacer, and a source/drain structure. The gate structure is on the semiconductor substrate. The silicon oxycarbonitride spacer is on a sidewall of the gate structure. The silicon oxycarbide spacer is on a sidewall of the silicon oxycarbonitride spacer. The silicon nitride spacer is on a sidewall of the silicon oxycarbide spacer, in which an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer. The source/drain structure is on the semiconductor substrate and adjacent to the gate structure.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Liang PAN, Yung-Tzu CHEN, Chung-Chieh LEE, Yung-Chang HSU, Chia-Yang HUNG, Po-Chuan WANG, Guan-Xuan CHEN, Huan-Just LIN
  • Publication number: 20240387517
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20240387646
    Abstract: A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chuan Wang, Chia-Yang Hung, Sheng-Liang Pan
  • Publication number: 20240387178
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: 12148620
    Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Jyun Wu, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20240379378
    Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Publication number: 20240379344
    Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin