Abstract: Provided are a fibroblast activation protein inhibitor (FAPI) dimer compound, an FAPI dimer-based positron emission tomography (PET) imaging agent for tumor diagnosis, and a preparation method and use thereof. An amphiphilic polyethylene glycol (PEG) chain and a dimerized structure of FAPI in the FAPI dimer compound with a structure shown in formula I can improve the in vivo kinetic properties of the compound and prolong a residence time of the compound in a tumor, thereby improving the uptake and imaging effects in the tumor. The accurate tumor diagnosis can be achieved by labeling the FAPI dimer compound with a diagnostic nuclide (68Ga), which has promising application prospects in PET imaging for diagnosis and in the preparation of a therapeutic nuclide (such as 177Lu or 90Y)-labeled drug for treating a FAP-?-expressing tumor.

Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.

Abstract: A rubber preforming apparatus includes a direct drive motor unit slidably disposed on a base unit. The direct drive motor unit includes a drive motor and a deceleration mechanism. The deceleration mechanism includes an input shaft coupling and an output shaft coupling axially aligned with and co-rotatably connected to the input shaft coupling. A drive spindle of the drive motor is inserted into and rotating together with the input shaft coupling. An extruder casing is disposed adjacent to the output shaft coupling and has a squeezing space. An extruder screw is disposed in the squeezing space, and includes a screw shaft with one end coaxially inserted into and rotating together with the output shaft coupling.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

Abstract: Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the string. However, there is a delay in charging up a drain end of the channel. A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage. When the reference voltage is reached, a voltage of the select gate transistor at the drain end of the string can be floated. This avoids unintentional programming of the select gate transistor which could otherwise occur if the voltage was floated to soon. Also, a substrate voltage may be ramped up to a first detected level before being ramped up to a second, final level.

Abstract: A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.