Patents by Inventor Liang Wu

Liang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11913772
    Abstract: The present disclosure is directed to a metrology system having 3-dimensional sensors for thickness measurements of semiconductor elements, and methods for taking the thickness measurements. In an aspect, the 3-dimensional sensor may be a single or dual 3-dimensional profiler that may scan across the top and bottom surfaces of an element to obtain a thickness measurement. In another aspect, the method may be used to measure a gap between elements that have assembled together.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Jianyong Mo, V Wade Singleton, Yiren Wu, Liang Zhang, David Wasinger
  • Patent number: 11917772
    Abstract: A power supply with a separable communication module includes a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module includes a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface, and a second state of detaching from the first interface.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 27, 2024
    Assignee: COTEK ELECTRONIC IND. CO., LTD.
    Inventors: Chun-Wei Wu, Ta-Chang Wei, Chung-Liang Tsai, Shou-Cheng Yeh
  • Publication number: 20240063817
    Abstract: An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Shaw Yuan, Zong Liang Wu, David Barr, Shachar Kons
  • Patent number: 11908136
    Abstract: A respiratory status classifying method is for classifying as one of at least two respiratory statuses and includes an original physiological parameter inputting step, an original chest image inputting step, a characteristic physiological parameter generating step, a characteristic chest image generating step, a training step and a classifier generating step. The characteristic chest image generating step includes processing at least a part of the original chest images, segmenting images of a left lung, a right lung and a heart from each of the original chest images that are processed, and enhancing image data of the images being segmented, so as to generate a plurality of characteristic chest images. The training step includes training two respiratory status classifiers using a plurality of characteristic physiological parameters and the characteristic chest images by at least one machine learning algorithm.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: February 20, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Ming-Cheng Chan, Kai-Chih Pai, Wen-Cheng Chao, Yu-Jen Huang, Chieh-Liang Wu, Min-Shian Wang, Chien-Lun Liao, Ta-Chun Hung, Yan-Nan Lin, Hui-Chiao Yang, Ruey-Kai Sheu, Lun-Chi Chen
  • Patent number: 11892923
    Abstract: A method for testing electronic products implemented in an electronic device includes selecting a serial port connected with a slave device in serial communication with a product under test. An activation instruction is transmitted to the slave device, and the electronic product is started through the slave device. Data stored in at least one register of the electronic product and a state of the electronic product is obtained and a capacitance of at least one capacitor in the electronic product is measured. When the electronic product is found to be in an abnormal state, determining a cause of abnormality according to data of the electronic product and the capacitance of the at least one capacitor.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 6, 2024
    Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.
    Inventor: Jia-Liang Wu
  • Patent number: 11888454
    Abstract: A blocking signal cancellation low noise amplifier system includes a first low noise amplifier, a second low noise amplifier, a blocking signal extraction and bias generation circuit, a bias switching circuit, and a bias switching signal generating circuit. The first low noise amplifier is used for dynamic input matching, and the first low noise amplifier receives an input signal and outputs it after amplifying. The blocking signal extraction and bias generation circuit is used to extract a blocking signal from the output signal of the first low noise amplifier, and output a DC voltage signal. The bias switching circuit is used to switch the first low noise amplifier between a blocking mode and a small signal mode. The bias switching signal generating circuit is used to compare the DC bias voltage signal VB2 with a preset reference voltage signal Vref.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: January 30, 2024
    Assignee: THE CHINESE UNIVERSITY OF HONG KONG, SHENZHEN
    Inventors: Liang Wu, Yifu Li, Xiaoping Wu, Shiyuan Zheng
  • Publication number: 20240018512
    Abstract: A method for analyzing cell epigenomics from multiple dimensions. The method comprises the following steps: by using ChiTag transposase and conventional Tn5 transposase in cells, respectively embedding different linker sequences, and achieving common analysis of information of a chromatin open region and information of a specific protein binding sequence on a cellular level. The method has important application prospects in aspects such as study of development and/or disease related cell population heterogeneity, drawing of a cell map, analysis of tumor cells having different clinical characteristics, and clinical study of evolution and/or metastasis of tumor cells.
    Type: Application
    Filed: September 16, 2020
    Publication date: January 18, 2024
    Inventors: Chunqing Wang, Liang Wu, Zihao Li, Yu Zhong, Yaling Huang, Yue Yuan, Chuanyu Liu
  • Publication number: 20240003515
    Abstract: A lens and light source module include: a light receiving surface; a light distribution surface, along the optical axis direction set opposite to the light receiving surface; light receiving surface away from the optical axis center region to form N groups of projection, where N?1; each with a first incident surface and a first reflective surface. The first incident surface is adapted to refracting light to the first reflective surface; the first reflective surface is adapted to reflecting light to a light distribution surface and refracting light to a display by the light distribution surface. The lens provided by the present invention enables the majority of light to be directed to the shelf in a targeted manner, which is conducive to achieving balanced light distribution and enhancing light efficiency.
    Type: Application
    Filed: June 16, 2023
    Publication date: January 4, 2024
    Inventors: Zuping He, Jun Yang, Liang Wu, Jianguo Dong, Kai Xu
  • Publication number: 20240006311
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a second substrate. The first substrate includes a first semiconductor layer, including a first trench isolation that extends through a portion of the first substrate layer; and a first interconnect structure, disposed over the first semiconductor layer. The second substrate includes a second semiconductor layer, including a plurality of semiconductor islands and surrounded by at least a second isolation penetrating the second semiconductor layer; a second interconnect structure, disposed over the second substrate layer and bonded to the first interconnect structure; and a dielectric layer, disposed over the second semiconductor layer opposite to the second interconnect structure. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: July 3, 2022
    Publication date: January 4, 2024
    Inventors: KUAN-LIANG LIU, CHUNG-LIANG CHENG, YEN LIANG WU, CHUNG-YUAN LI, YA CHUN TENG
  • Patent number: 11864391
    Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Te-Wei Yeh, Chien-Liang Wu
  • Publication number: 20230420126
    Abstract: A bloodstream infection predicting system and a method thereof are proposed. The memory unit stores a plurality of historical medical data, the real-time data to be tested and a machine learning algorithm. The processor is configured to implement a bloodstream infection predicting method. The bloodstream infection predicting method includes reading the historical medical data from the memory unit, training the historical medical data to generate a bloodstream infection prediction model, reading the real-time data to be tested of the patient from the memory unit, and inputting the real-time data to be tested into the bloodstream infection prediction model to generate the bloodstream infection risk probability. The real-time data to be tested includes an intensive care unit detecting data and a blood inspection data of the patient. The intensive care unit detecting data and the blood inspection data are detected during a feature window time interval.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Inventors: Chieh-Liang WU, Po-Yu LIU, Kai-Chih PAI, Lai-Shiun LAI, Min-Shian WANG, Ruey-Kai SHEU, Lun-Chi CHEN
  • Patent number: 11854632
    Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: December 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chien-Liang Wu, Wen-Kai Lin, Te-Wei Yeh, Sheng-Yuan Hsueh, Chi-Horn Pai
  • Patent number: 11843318
    Abstract: This application discloses a converter and a power adapter, to reduce an energy loss of the power adapter. The converter includes: a DC power supply, a primary power transistor, an auxiliary power transistor, a first capacitor, a transformer, and a control circuit. The first capacitor is connected in series to the transformer to form a series circuit, the series circuit is connected in parallel to a first terminal and a second terminal of the auxiliary power transistor. The control circuit is configured to: when an excitation current in the transformer is in a continuous state, regulate a target voltage to a preset voltage threshold, and control the primary power transistor to be turned on when first dead time ends, where the target voltage is a voltage between the first terminal of the primary power transistor and the ground.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: December 12, 2023
    Assignee: HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD.
    Inventors: Gun Yang, Liang Wu, Zuwei He
  • Publication number: 20230381935
    Abstract: A removal tool for a ball joint contains: a first support arm, a second support arm, a first engagement post, a second engagement post, a first connector, and a second connector. The first support arm includes a rotatable fixing member and the first connector. The second support arm includes a rotatable screwing member and the second connector. The first support arm further includes a first fitting sleeve, and the second support arm includes a second fitting sleeve. The second engagement post includes a first threaded section, and the second engagement post includes a second threaded section, a spiral rotation direction of the first threaded section is opposite to a spiral rotation direction of the second threaded section.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventor: PI-LIANG WU
  • Publication number: 20230387815
    Abstract: This application discloses a direct current to direct current converter, an electronic device, and a charger, to strike a balance between efficiency and a voltage conversion range. The direct current to direct current converter includes a switch circuit, an auxiliary circuit, a transformer, and a first half-wave rectifier circuit. The transformer is configured to: when the switch circuit is in a first state, store first electric energy transmitted by the auxiliary circuit; and when the switch circuit is in a second state, receive second electric energy transmitted by the auxiliary circuit, and output the received second electric energy and the stored first electric energy to the first half-wave rectifier circuit.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Liang Wu, Shengyong Dai
  • Publication number: 20230380742
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 30, 2023
    Inventors: Chun-Te HUANG, Kai-Chih PAI, Tsai-Jung WANG, Min-Shian WANG, Yan-Nan LIN, Cheng-Hsu CHEN, Chun-Ming LAI, Ruey-Kai SHEU, Lun-Chi CHEN, Chieh-Liang WU, Chien-Lun LIAO, Ta-Chun HUNG, Chien-Chung HUANG, Chia-Tien HSU, Shang-Feng TSAI
  • Patent number: 11831329
    Abstract: An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: November 28, 2023
    Assignee: Entropic Communications, LLC
    Inventors: Shaw Yuan, Zong Liang Wu, David Barr, Shachar Kons
  • Publication number: 20230377225
    Abstract: A method for training an image editing model includes steps described below. Covering processing is performed on a region of interest determined in an original image so that a background image sample is formed, and content corresponding to the region of interest is determined as a sample of content of interest; the background image sample and the sample of the content of interest are input into an image editing model; fusion processing is performed on a background image feature and a feature of the region of interest by using the image editing model so that a fusion feature is formed; an image reconstruction operation is performed according to the fusion feature by using the image editing model so that a reconstructed image is output; and optimization training is performed on the image editing model according to a loss relationship between the reconstructed image and the original image.
    Type: Application
    Filed: March 14, 2023
    Publication date: November 23, 2023
    Inventors: Chengquan ZHANG, Yuechen YU, Liang WU
  • Patent number: D1007034
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: December 5, 2023
    Assignee: Self Electronics Co., Ltd.
    Inventors: Jun Yang, Jianguo Dong, Kai Xu, Liang Wu, Hui Chen
  • Patent number: D1007738
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: December 12, 2023
    Assignee: Self Electronics Co., Ltd.
    Inventors: Jun Yang, Jianguo Dong, Kai Xu, Liang Wu, Hui Chen