Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: A system for electrically coupling a garment to a mating object and manufacture method thereof, the system comprising: a fabric interlayer of the garment including a set of ports; an electronics substrate having a first surface adjacent to a second side of the fabric interlayer and including a set of vias through a thickness of the electronics substrate, aligned with the set of ports, and a set of contacts at a second surface opposing the first surface; a mount assembly having a third surface adjacent to the second surface of the electronics substrate and including a set of holes aligned with the set of vias and the set of ports, as well as a set of openings that correspond to and receive portions of the set of contacts, and a fourth surface opposing the third surface and defining a cavity configured to receive and electrically interface the mating object to the electronics substrate; and a set of fasteners that 1) compress the backing plate, the fabric interlayer, the electronics substrate, and the mount ass

Abstract: A nozzle auto-cleaning device and a nozzle auto-cleaning method are disclosed. The nozzle auto-cleaning device includes a base and a cleaning piece feeding unit disposed on the base, the base has a bearing surface on which the cleaning piece feeding unit is disposed, the cleaning piece feeding unit is configured to transport a cleaning piece installed inside the nozzle auto-cleaning device along a first direction intersected with the bearing surface so that a first portion of the cleaning piece is protruded in a direction away from the bearing surface and inserted into a nozzle, and the base is configured to move along at least one direction of the first direction, as well as a second direction and a third direction intersected in a plane of the bearing surface, so as to drive the first portion of the cleaning piece to move inside the nozzle.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a plurality of gate structures disposed over a substrate. A plurality of metal structures continuously extend from lower surfaces contacting the plurality of gate structures to upper surfaces contacting one or more interconnects within an overlying conductive interconnect layer. The plurality of metal structures are arranged at a first pitch that is larger than a second pitch of the plurality of gate structures.

Abstract: A system for electrically coupling a garment to a mating object and manufacture method thereof, the system comprising: a fabric interlayer of the garment including a set of ports; an electronics substrate having a first surface adjacent to a second side of the fabric interlayer and including a set of vias through a thickness of the electronics substrate, aligned with the set of ports, and a set of contacts at a second surface opposing the first surface; a mount assembly having a third surface adjacent to the second surface of the electronics substrate and including a set of holes aligned with the set of vias and the set of ports, as well as a set of openings that correspond to and receive portions of the set of contacts, and a fourth surface opposing the third surface and defining a cavity configured to receive and electrically interface the mating object to the electronics substrate; and a set of fasteners that 1) compress the backing plate, the fabric interlayer, the electronics substrate, and the mount ass

Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over an underlying structure disposed on a substrate. A planarization resistance layer is formed over the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the planarization resistance layer. A planarization operation is performed on the second dielectric layer, the planarization resistance layer and the first dielectric layer. The planarization resistance film is made of a material different from the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.

Abstract: An athletic garment includes sensors at different locations of the garment. The sensors are electrically coupled to a processing unit and/or a power source via one or more conduits that are printed onto the garment. The conduits are designed for improved flexibility to accommodate stretching in the garment that occurs as a user wearing the garment performs an exercise and for improved durability to resist corrosion due to friction, sweat, or washing of the garment. In one embodiment, the conduits are designed for decreased stress concentrations at seams of the garment. In one embodiment, the conduits are designed to create a conductive pathway between different surfaces of the garment to electrically couple sensors on a first side (skin side) of the garment and a processing unit and/or a power source on a second side (outer side) of the garment.

Abstract: A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that includes an electrical connection between the two active regions, a second contact layer that includes a connection between two gate lines, and a gate contact layer that provides connections to the gate lines.

Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.

Abstract: The present invention provides an apparatus for rapid ellipsometry. The apparatus contains a light source, a polarizer, a sample stage, an integrated polarization analyzer, and a detector assembly. The light emitted by light source is polarized by the polarizer and shines on the sample mounted on sample stage. The light is reflected from the sample surface and passes through the integrated polarization analyzer. The analyzer contains multiple polarizers with different polarization angles from 0 to 180 degrees for transmitting light from the sample. The detector assembly includes multiple detectors corresponding one-to-one with the multiple polarizers, for independently determining the light intensity transmitted by each polarizer. The current invention provides a rapid ellipsometry apparatus that is highly efficient, with the fastest acquisition time down to nanosecond scale for obtaining dynamic parameters of the sample.

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: A nozzle auto-cleaning device and a nozzle auto-cleaning method are disclosed. The nozzle auto-cleaning device includes a base and a cleaning piece feeding unit disposed on the base, the base has a bearing surface on which the cleaning piece feeding unit is disposed, the cleaning piece feeding unit is configured to transport a cleaning piece installed inside the nozzle auto-cleaning device along a first direction intersected with the bearing surface so that a first portion of the cleaning piece is protruded in a direction away from the bearing surface and inserted into a nozzle, and the base is configured to move along at least one direction of the first direction, as well as a second direction and a third direction intersected in a plane of the bearing surface, so as to drive the first portion of the cleaning piece to move inside the nozzle.

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: A garment can be manufactured by bonding an adhesive to a first layer of fabric and a second layer of fabric. Holes are cut into each layer of fabric to accommodate the integration of sensors and a processing unit mount. Conductive thread embroidered onto a support layer is bonded to the adhesive of the second layer of fabric. The support layer is removed such that the conductive thread remains bonded to the adhesive. The layers of fabric are bonded together such that the conductive thread is coupled between the two layers of adhesive. A back plate is added to the layers of fabric to provide structural support for the mount. The conductive thread is exposed within each hole, and the mount and sensors can be coupled within the holes such that an electrical connection is established between the mount and at least one sensor via the conductive thread.

Abstract: Disclosed is a method for recoating an RTV anti-pollution flashover coating on an insulator coated with the RTV anti-pollution flashover coating. The insulator includes an insulator body, a steel cap connected to an upper surface of the insulator body, and a steel pin connected to a lower surface of the insulator body. The method includes: (1) wiping off dirt on a surface of the insulator; (2) determining whether the insulator can be recoated; (3) performing coating by using an RTV anti-pollution flashover coating with the content of solid being 55%-65%. After coating is performed, a newly coated anti-pollution flashover coating can be closely adhered to a surface of the insulator, swelling does not occur, adhesion of the coating with respect to the insulator is not reduced, the hydrophobicity of the surface is recovered, and non-reduction of a pollution flashover voltage of the insulator is ensured.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over an underlying structure disposed on a substrate. A planarization resistance layer is formed over the first dielectric layer. A second dielectric layer is formed over the first dielectric layer and the planarization resistance layer. A planarization operation is performed on the second dielectric layer, the planarization resistance layer and the first dielectric layer. The planarization resistance film is made of a material different from the first dielectric layer.

Abstract: A liquid knife cleaning apparatus and a liquid knife are provided. The liquid knife cleaning apparatus includes: a frame configured to be arranged on the liquid knife and be capable of reciprocating in an extending direction of the knife edge; a cleaning blade configured to extend into the knife edge of the liquid knife and be capable of reciprocating inside the knife edge under the driving of the frame to clean the knife edge, the cleaning blade being arranged on the frame; and a movable mechanism configured to control the frame to reciprocate on the liquid knife in the extending direction of the knife edge, the frame being connected to the movable mechanism.

Abstract: A method for ameliorating corner rounding effects in a photolithographic process is provided. A semiconductor workpiece having an active device region is provided, and a photoresist layer is formed over the semiconductor workpiece. A mask is provided for patterning for the photoresist layer, wherein the mask comprises pattern having a sharp corner associated with the active device region. The sharp corner is separated from the active device region by a first distance in a first direction and a second distance in a second direction, wherein the first distance meets a minimum criteria for the photolithographic process, and wherein the second distance is greater than the first distance. The photoresist layer is then exposed to a radiation source, and the radiation source patterns the photoresist layer through the mask, defining an exposure region on the semiconductor workpiece having a rounded corner associated with the sharp corner.