Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein, in several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the memory regions. A stack extends across the memory regions and the intermediate region. The stack includes alternating conductive levels and insulative levels. Channel-material-pillars are arranged within the memory regions. Memory-block-regions extend longitudinally across the memory regions and the intermediate region. Staircase regions are within the intermediate region. Each of the staircase regions laterally overlaps two of the memory-block-regions. First panel regions extend longitudinally across at least portions of the staircase regions. Second panel regions extend longitudinally and provide lateral separation between adjacent memory-block-regions. The second panel regions are of laterally different dimensions than the first panel regions and/or are compositionally different than the first panel regions.

Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions.

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an insulator tier above the wordline tiers. The insulator tier comprises first insulator material comprising silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus. The first insulator material is patterned to form first horizontally-elongated trenches in the insulator tier. Second insulator material is formed in the first trenches along sidewalls of the first insulator material. The second insulator material is of different composition from that of the first insulator material and narrows the first trenches. After forming the second insulator material, second horizontally-elongated trenches are formed through the insulative tiers and the wordline tiers. The second trenches are horizontally along the narrowed first trenches laterally between and below the second insulator material.

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.