Abstract: A memory die is bonded to a logic die on a wafer by die-to-wafer bonding. The logic die may include surface metal pads having first planar horizontal surfaces located within a horizontal plane including a bonding interface and located within an area not overlapping with an area of the memory die. Alternatively or additionally, electrically conductive paths may be present between sense amplifiers in the logic die and first bit lines in the memory die. The electrically conductive paths may include second bit lines located in the logic die and laterally extending from within an area overlapping with the area of the memory die to an area not overlapping with the area of the memory die in a plan view. One or more memory die can be attached to the logic die.

Abstract: Provided is an amorphous silicon thin-film transistor including an amorphous silicon semiconductor layer, a source electrode, and a drain electrode that are successively disposed on a base substrate. Ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer. A concentration of the ions in a surface region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer is greater than or equal to 5*10{circumflex over (?)}20 atoms/cc.

Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.

Abstract: The display substrate, display device and motherboard include a first base substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel electrodes, a plurality of first light-shielding structures, and a plurality of second light-shielding structures; where the orthographic projections of the plurality of first light-shielding structures on the first base substrate and the orthographic projections of the plurality of second signal lines on the first base substrate have areas that do not overlap with each other; a plurality of second light-shielding structures arranged between the layers where the plurality of first signal lines and the plurality of second signal lines are located and the first base substrate; an orthographic projection of one first signal line on the first base substrate is on a side of an orthographic projection of a symmetry axis extending along the first direction of one second light-shielding structure.

Abstract: The display substrate, display device and motherboard provided in the present disclosure include a first base substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of pixel electrodes, and the orthographic projection of the pixel electrodes on the first base substrate is within the orthographic projection of the area defined by the intersection of each first signal line and each second signal line; first light-shielding structures are located above the layer where the pixel electrodes are located, each first light-shielding structure extends in the second direction and is arranged along the first direction, the orthographic projections of the first light-shielding structures on the substrate of the first substrate is within the orthographic projection of gaps between the columns of pixel electrodes extending in the second direction, and has an area that does not overlap with the orthographic projection of the second signal line.

Abstract: Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

Abstract: The display substrate, display device and motherboard provided in the present disclosure include a first base substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of pixel electrodes, and the orthographic projection of the pixel electrodes on the first base substrate is within the orthographic projection of the area defined by the intersection of each first signal line and each second signal line; first light-shielding structures are located above the layer where the pixel electrodes are located, each first light-shielding structure extends in the second direction and is arranged along the first direction, the orthographic projections of the first light-shielding structures on the substrate of the first substrate is within the orthographic projection of gaps between the columns of pixel electrodes extending in the second direction, and has an area that does not overlap with the orthographic projection of the second signal line.

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

Abstract: The present disclosure provides a thin film transistor, a display substrate and a display device, and belongs to the field of display technology. The thin film transistor of the present disclosure includes: a base, and a gate, an active layer, a source and a drain located on the base, where the gate includes a first gate and a second gate which are sequentially provided on the base and are electrically connected to each other; the active layer is located between the first gate and the second gate, and orthographic projections of the first gate and the second gate on the base are partially overlapped with an orthographic projection of the active layer on the base, and the orthographic projections of the first gate and the second gate on the base are partially overlapped with each other.

Abstract: A method for estimating a beam domain channel in a spatial non-stationary massive MIMO system includes constructing a beam domain channel model for the spatial non-stationary massive MIMO system by using a visibility region; transforming a problem for estimating the beam domain channel into a problem for reconstructing a sparse channel based on a sparsity of beam domain channel and an influence of power leakage; proposing a beam domain structure-based sparsity adaptive matching pursuit scheme according to a cross-block sparse structure and a power ratio threshold of the beam domain channel; and verifying that the proposed scheme has a lower pilot overhead, a higher accuracy and a higher effectiveness compared to the traditional schemes in simulation results. The method can be effectively applied to communication channel estimation with non-stationary characteristics, and has obvious advantages in estimation accuracy and complexity.

Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

Abstract: Provided is an amorphous silicon thin-film transistor including an amorphous silicon semiconductor layer, a source electrode, and a drain electrode that are successively disposed on a base substrate. Ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer. A concentration of the ions in a surface region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer is greater than or equal to 5*10{circumflex over (?)}20 atoms/cc.

Abstract: A device of updating library required by a testing program for testing and a method thereof are disclosed. A system configuration file of an old testing device is modified to make the old testing device enter a testing mode when booting, so that library supporting the testing program of an application is updated in the testing mode; when the application is executed, the testing program is connected to the to-be-tested device for performing testing, so that the old testing device can be updated through network without dedicated hardware, and the technical effect of reducing the time and labor cost for updating the old testing device can be achieved.

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

Abstract: A device of updating library required by a testing program for testing and a method thereof are disclosed. A system configuration file of an old testing device is modified to make the old testing device enter a testing mode when booting, so that library supporting the testing program of an application is updated in the testing mode; when the application is executed, the testing program is connected to the to-be-tested device for performing testing, so that the old testing device can be updated through network without dedicated hardware, and the technical effect of reducing the time and labor cost for updating the old testing device can be achieved.

Abstract: Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

Abstract: Provided are a display substrate motherboard and manufacturing method thereof, a display substrate and a display apparatus. The display substrate motherboard includes a substrate, a display substrate area on the substrate, and a mark area on the periphery of the display substrate area. The display substrate motherboard also includes a thin film transistor disposed in the display substrate area, a mark structure disposed in the mark area and a planarization layer disposed on one side of the thin film transistor away from the substrate, and the planarization layer includes a groove which is disposed at the corresponding position of the mark structure and extends along a direction close to the substrate, and an orthographic projection of the groove on the substrate covers an orthographic projection of the mark structure on the substrate.

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.