Abstract: The present disclosure relates to the field of image definition recognition, and discloses a logging image definition recognition method and device, medium and electronic equipment. The method comprises: establishing a logging image sample library comprising a plurality of logging images; acquiring actual definition information corresponding to the respective logging images; acquiring a plurality of definitions corresponding to the respective logging images; determining target weights corresponding to the respective target image definition determination algorithms according to the plurality of definitions and the actual definition information corresponding to the respective logging images; and determining a definition of a target logging image by the respective target image definition determination algorithms and the target weights corresponding to the respective target image definition determination algorithms.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: A method for preparing a three-dimensional carbon nanotube composite structure comprises: providing a substrate; subjecting the substrate to nickel ion modification treatment to form at least one nickel ion nuclear seed on the substrate; providing a hydrogen gas to pass through the substrate and heating the substrate to a reduction temperature for reducing the nickel ion nuclear seed by the hydrogen gas at the reduction temperature; and supplying a carbon source gas and a protective gas to pass through the substrate and heating the substrate to a growth temperature so that the carbon atoms generated by the carbon source gas through the catalytic cracking of the nickel ion nuclear seed are deposited on the bottom of the nickel ion nuclear seed to form a carbon nanotube gradually, wherein the growth temperature is greater than or equal to the reduction temperature. The three-dimensional carbon nanotube composite structure prepared by the method and its application are also disclosed.

Abstract: A system and method for tracking non-geo synchronous orbit satellites on orbiting planes of regular motion patterns. The method includes providing a first satellites moving in a direction descending in latitude in first orbital planes and a second satellites moving in a direction ascending in latitude in second orbital planes; steering an antenna to an antenna tilt ? from normal with a single axis mechanism lined up with a first axis; scanning, electronically, with a linear array at a scan angle ? along a second axis; and locking to a signal from a handed-from satellite from the first satellites, where the first axis is angled from the second axis, the steering along the first axis and the scanning along the second axis jointly track the handed-from satellite, the first orbits seem parallel, the second orbits seem parallel, and the first orbits seem aligned with the antenna tilt ?. A handoff between the first satellites may use one of the second satellites as a steppingstone.

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.

Abstract: Systems and methods for Internet access control are presented. A third-party application is hosted by a third-party server on the Internet. The third-party application has third-party data of a user. An Internet access control device detects an Internet access by the user to a target server on the Internet. The Internet access control device allows or blocks the Internet access depending on whether the Internet access is permitted or prohibited based on the third-party data.

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.

Abstract: A device of updating library required by a testing program for testing and a method thereof are disclosed. A system configuration file of an old testing device is modified to make the old testing device enter a testing mode when booting, so that library supporting the testing program of an application is updated in the testing mode; when the application is executed, the testing program is connected to the to-be-tested device for performing testing, so that the old testing device can be updated through network without dedicated hardware, and the technical effect of reducing the time and labor cost for updating the old testing device can be achieved.

Abstract: Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

Abstract: Provided are a display substrate motherboard and manufacturing method thereof, a display substrate and a display apparatus. The display substrate motherboard includes a substrate, a display substrate area on the substrate, and a mark area on the periphery of the display substrate area. The display substrate motherboard also includes a thin film transistor disposed in the display substrate area, a mark structure disposed in the mark area and a planarization layer disposed on one side of the thin film transistor away from the substrate, and the planarization layer includes a groove which is disposed at the corresponding position of the mark structure and extends along a direction close to the substrate, and an orthographic projection of the groove on the substrate covers an orthographic projection of the mark structure on the substrate.

Abstract: A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a first electrode located on the base substrate and including a pad portion, the pad portion including a first surface and a second surface, the second surface being closer to the base substrate than the first surface; a first insulation layer located on the first electrode and including a first via hole; a second insulation layer located on the first insulation layer and including a second via hole; and a second electrode located on the second insulation layer; the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.

Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.

Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.