Patents by Inventor Lin Hou

Lin Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230008286
    Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Inventors: Lin HOU, Peter RABKIN, Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Masaaki HIGASHITANI
  • Patent number: 11547943
    Abstract: An apparatus and method for providing social network content in an online game is disclosed herein. Content is obtained from a social network site and is displayed within the game. The game also provides a mechanism for the user of the game to generate content to the posted within the social network from within the game. Such generated content is automatically posted in the social network for a recipient specified by the user.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 10, 2023
    Assignee: Zynga Inc.
    Inventors: Jinming Cao, Lin Hou, Chao Guo, Xingguang Yu, Huiqiang Liu, Kerry Yang, Lin Lin
  • Publication number: 20220406945
    Abstract: The present disclosure provides a thin film transistor, a display substrate and a display device, and belongs to the field of display technology. The thin film transistor of the present disclosure includes: a base, and a gate, an active layer, a source and a drain located on the base, where the gate includes a first gate and a second gate which are sequentially provided on the base and are electrically connected to each other; the active layer is located between the first gate and the second gate, and orthographic projections of the first gate and the second gate on the base are partially overlapped with an orthographic projection of the active layer on the base, and the orthographic projections of the first gate and the second gate on the base are partially overlapped with each other.
    Type: Application
    Filed: May 21, 2021
    Publication date: December 22, 2022
    Inventors: Chenglong WANG, Yezhou FANG, Feng LI, Lei YAO, Lei YAN, Kai LI, Lin HOU, Xiaogang ZHU, Yun GAO, Yanzhao PENG, Teng YE, Hua YANG
  • Publication number: 20220350196
    Abstract: The present disclosure discloses a color filter substrate and a method for manufacturing the same, a display panel, and a display device, which relates to the field of display technologies. A black matrix layer in the color filter substrate includes a first film layer and a second film layer. As a material of the first film layer is different from a material of the second film layer, at least one of the first film layer and the second film layer is prepared without using a resin adhesive, and then the resin adhesive remaining in at least one through-hole of the first through-holes of the first film layer and the second through-holes of the second film layer can be reduced, and the display effect of the display device is ensured.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 3, 2022
    Inventors: Lei YAO, Yezhou FANG, Feng LI, Lei YAN, Kai LI, Chenglong WANG, Teng YE, Lin HOU, Xiaofang LI
  • Publication number: 20220352104
    Abstract: A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: Lin HOU, Peter RABKIN, Masaaki HIGASHITANI
  • Patent number: 11448929
    Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 20, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Lei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Jinjin Xue, Fang Yan, Xiaowen Si, Lin Hou, Zhixuan Guo, Yuanbo Li, Xiaofang Li
  • Patent number: 11424215
    Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: August 23, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Publication number: 20220246562
    Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.
    Type: Application
    Filed: February 4, 2021
    Publication date: August 4, 2022
    Inventors: Lin HOU, Peter RABKIN, Masaaki HIGASHITANI
  • Patent number: 11404025
    Abstract: A video processing system includes an input port and a video processing circuit. The input port obtains device information of a display panel. The video processing circuit obtains an input frame and the device information, configures an image enhancement operation according to the device information, generates an output frame by performing the image enhancement operation upon the input frame, and transmits the output frame to the display panel for video playback.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: August 2, 2022
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wen Goo, Yu-Cheng Tseng, Yu-Lin Hou, Kuo-Chiang Lo, Chia-Da Lee, Tung-Chien Chen
  • Patent number: 11398092
    Abstract: A parking detection method based on visual difference includes: obtaining a video frame of a predetermined monitoring area captured by each camera in real time, and labeling the video frame corresponding to each camera with time information of a current moment; determining vehicle information of a to-be-detected vehicle in each video frame labeled with the time information through a predetermined convolutional neural network model; determining feature point information of the to-be-detected vehicle in each video frame according to the vehicle information of the to-be-detected vehicle in each video frame; calculating a position relationship between the to-be-detected vehicle in each video frame and respective corresponding camera, and constructing current three-dimensional coordinates of the to-be-detected vehicle according to the position relationship; and determining a parking status of the to-be-detected vehicle according to the current three-dimensional coordinates of the to-be-detected vehicle.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: July 26, 2022
    Assignee: INTELLIGENT INTER CONNECTION TECHNOLOGY CO., LTD.
    Inventors: Jun Yan, Lin Hou
  • Patent number: 11362061
    Abstract: A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: June 14, 2022
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Lin Hou, Jaber Derakhshandeh, Eric Beyne, Ingrid De Wolf, Giovanni Capuz
  • Publication number: 20220173071
    Abstract: A first bonding unit is provided, which includes a first substrate, a first passivation dielectric layer, and first bonding pads. A second bonding unit is provided, which includes a second substrate, a second passivation dielectric layer, and second bonding pads including bonding pillar structures. Solder material portions are formed on physically exposed surfaces of the first bonding pads. The second bonding unit is attached to the first bonding unit by bonding the at least one of the bonding pillar structures to a respective solder material portion.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: Lin HOU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI
  • Publication number: 20220173050
    Abstract: Provided are a display substrate motherboard and manufacturing method thereof, a display substrate and a display apparatus. The display substrate motherboard includes a substrate, a display substrate area on the substrate, and a mark area on the periphery of the display substrate area. The display substrate motherboard also includes a thin film transistor disposed in the display substrate area, a mark structure disposed in the mark area and a planarization layer disposed on one side of the thin film transistor away from the substrate, and the planarization layer includes a groove which is disposed at the corresponding position of the mark structure and extends along a direction close to the substrate, and an orthographic projection of the groove on the substrate covers an orthographic projection of the mark structure on the substrate.
    Type: Application
    Filed: September 24, 2021
    Publication date: June 2, 2022
    Inventors: Lei YAO, Feng LI, Lei YAN, Kai LI, Chenglong WANG, Teng YE, Lin HOU, Xiaofang LI
  • Patent number: 11348901
    Abstract: A first bonding unit is provided, which includes a first substrate, a first passivation dielectric layer, and first bonding pads. A second bonding unit is provided, which includes a second substrate, a second passivation dielectric layer, and second bonding pads including bonding pillar structures. Solder material portions are formed on physically exposed surfaces of the first bonding pads. The second bonding unit is attached to the first bonding unit by bonding the at least one of the bonding pillar structures to a respective solder material portion.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 31, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Publication number: 20220149002
    Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.
    Type: Application
    Filed: November 10, 2020
    Publication date: May 12, 2022
    Inventors: Lin HOU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI
  • Publication number: 20220093555
    Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventors: Lin HOU, Peter RABKIN, Yangyin CHEN, Masaaki HIGASHITANI, Rahul SHARANGPANI
  • Publication number: 20220044025
    Abstract: A parking detection method based on visual difference includes: obtaining a video frame of a predetermined monitoring area captured by each camera in real time, and labeling the video frame corresponding to each camera with time information of a current moment; determining vehicle information of a to-be-detected vehicle in each video frame labeled with the time information through a predetermined convolutional neural network model; determining feature point information of the to-be-detected vehicle in each video frame according to the vehicle information of the to-be-detected vehicle in each video frame; calculating a position relationship between the to-be-detected vehicle in each video frame and respective corresponding camera, and constructing current three-dimensional coordinates of the to-be-detected vehicle according to the position relationship; and determining a parking status of the to-be-detected vehicle according to the current three-dimensional coordinates of the to-be-detected vehicle.
    Type: Application
    Filed: November 26, 2020
    Publication date: February 10, 2022
    Applicant: INTELLIGENT INTER CONNECTION TECHNOLOGY CO., LTD.
    Inventors: Jun YAN, Lin HOU
  • Publication number: 20210378580
    Abstract: A brain wave monitoring system includes an electronic device and at least one electroencephalograph connected to the electronic device, each electroencephalograph includes 8 channels respectively connected to a corresponding electrode for receiving a brain wave signal. The electronic device scans a number of the at least one electroencephalograph and sequentially displays multiple channels of the at least one electroencephalograph according to an identifier of each of the at least one electroencephalograph. The brain wave monitoring system can automatically detect the number of electroencephalographs connected to the electronic device, and display the brain wave signals of all channels of all electroencephalographs according to the number of electroencephalographs and 8 channels of each electroencephalograph. The brain wave monitoring system can also prompt a guide message according to a channel impedance value and a signal quality index to assist a user improving a quality of the brain wave.
    Type: Application
    Filed: March 10, 2021
    Publication date: December 9, 2021
    Inventors: Chang-Hsin WENG, Wen-Hung LAN, Chung-Lin HOU
  • Publication number: 20210343747
    Abstract: An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a first electrode located on the base substrate and including a pad portion, the pad portion including a first surface and a second surface, the second surface being closer to the base substrate than the first surface; a first insulation layer located on the first electrode and including a first via hole; a second insulation layer located on the first insulation layer and including a second via hole; and a second electrode located on the second insulation layer; the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.
    Type: Application
    Filed: September 29, 2018
    Publication date: November 4, 2021
    Inventors: Fang YAN, Dawei SHI, Lei YAO, Zifeng WANG, Wentao WANG, Lu YANG, Haifeng XU, Xiaowen SI, Jinfeng WANG, Lei YAN, Jinjin XUE, Lin HOU
  • Publication number: 20210333608
    Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.
    Type: Application
    Filed: May 16, 2019
    Publication date: October 28, 2021
    Inventors: Lei YAO, Dawei SHI, Wentao WANG, Lu YANG, Haifeng XU, Lei YAN, Jinfeng WANG, Jinjin XUE, Fang YAN, Xiaowen SI, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI