Patents by Inventor Lin Hou

Lin Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327838
    Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 21, 2021
    Inventors: Lin HOU, Peter RABKIN, Masaaki HIGASHITANI, Ramy Nashed Bassely SAID
  • Publication number: 20210320075
    Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first metallic plates. First bonding pads including a respective one of the first metallic plates are formed. A first polymer material layer can be formed over the first bonding pads. A second semiconductor die including second bonding pads is bonded to the first bonding pads to form a bonded assembly.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventors: Lin HOU, Peter RABKIN, Masaaki HIGASHITANI, Ramy Nashed Bassely SAID
  • Patent number: 11121226
    Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 14, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Lei Yan, Feng Li, Yezhou Fang, Jun Fan, Lei Li, Yanyan Meng, Lei Yao, Jinjin Xue, Chenglong Wang, Jinfeng Wang, Lin Hou, Zhixuan Guo
  • Publication number: 20210249450
    Abstract: An array substrate and a method for manufacturing the same, and a display device are provided. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Inventors: Jinjin Xue, Dawei Shi, Feng Li, Lei Yao, Wentao Wang, Haifeng Xu, Lu Yang, Lin Hou, Jinfeng Wang, Mei Li, Yezhou Fang
  • Publication number: 20210217894
    Abstract: A CMOS thin film transistor, a method for manufacturing the same, and an array substrate are provided. The method includes: forming a semiconductor layer including an N-type region and a P-type region on a substrate, the N-type region is divided into a first region, a second region, a third region, a fourth region and a fifth region, the P-type region is divided into a sixth region, a seventh region and an eighth region; performing first N-type ion doping on the first region and the fifth region; performing first P-type ion doping on the N-type region; performing second P-type ion doping on the N-type region and the P-type region; performing second N-type ion doping on the first region, the second region, the fourth region, the fifth region, the sixth region and the eighth region; and performing third P-type ion doping on the sixth region and the eighth region.
    Type: Application
    Filed: December 25, 2019
    Publication date: July 15, 2021
    Inventors: Lei YAO, Yezhou FANG, Feng LI, Lei YAN, Jinjin XUE, Chenglong WANG, Yanyan MENG, Jinfeng WANG, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI
  • Patent number: 11031419
    Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 8, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinjin Xue, Dawei Shi, Feng Li, Lei Yao, Wentao Wang, Haifeng Xu, Lu Yang, Lin Hou, Jinfeng Wang, Mei Li, Yezhou Fang
  • Publication number: 20210157508
    Abstract: The present disclosure provides a test method, system, medium and device for a dual in-line memory module, the test method includes: obtaining a position of the dual in-line memory module on a server; modifying a protection mechanism after detecting a defective dual in-line memory module; testing each dual in-line memory module; storing the test result in a system event log of the baseboard management control module. The test method, system, medium and device for a dual in-line memory module of the present disclosure is to prevent the server from being shut down during the test of the dual in-line memory module, and timely discover the defective dual in-line memory module.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 27, 2021
    Applicants: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Lin HOU, Wei HUANG
  • Publication number: 20210020755
    Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.
    Type: Application
    Filed: January 29, 2019
    Publication date: January 21, 2021
    Inventors: Lei YAN, Feng LI, Yezhou FANG, Jun FAN, Lei LI, Yanyan MENG, Lei YAO, Jinjin XUE, Chenglong WANG, Jinfeng WANG, Lin HOU, Zhixuan GUO
  • Publication number: 20200402950
    Abstract: A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 24, 2020
    Inventors: Lin Hou, Jaber Derakhshandeh, Eric Beyne, Ingrid De Wolf, Giovanni Capuz
  • Publication number: 20200382363
    Abstract: Methods and systems for managing security in a cloud computing environment are provided. Exemplary methods include: gathering data about workloads and applications in the cloud computing environment; updating a graph database using the data, the graph database representing the workloads of the cloud computing environment as nodes and relationships between the workloads as edges; receiving a security template, the security template logically describing targets in the cloud computing environment to be protected and how to protect the targets; creating a security policy using the security template and information in the graph database; and deploying the security policy in the cloud computing environment.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Marc Woolward, Keith Stewart, Timothy Eades, Meng Xu, Myo Zarny, Matthew M. Williamson, Jason Parry, Hong Xiao, Hsisheng Wang, Cheng-Lin Hou
  • Publication number: 20200327864
    Abstract: A video processing system includes an input port and a video processing circuit. The input port obtains device information of a display panel. The video processing circuit obtains an input frame and the device information, configures an image enhancement operation according to the device information, generates an output frame by performing the image enhancement operation upon the input frame, and transmits the output frame to the display panel for video playback.
    Type: Application
    Filed: March 15, 2020
    Publication date: October 15, 2020
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wen Goo, Yu-Cheng Tseng, Yu-Lin Hou, Kuo-Chiang Lo, Chia-Da Lee, Tung-Chien Chen
  • Patent number: 10795228
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, in which a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 6, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Xiaowen Si, Fang Yan, Jinjin Xue, Lin Hou, Yuanbo Li, Zhixuan Guo, Xiaofang Li
  • Patent number: 10755634
    Abstract: A display driving circuit applied to a display includes a detection unit, a counting unit and an adjusting unit. The detection unit is configured to detect N pulses of an emission control signal of the display in a frame and define a frame porch interval increasing unit accordingly. The frame porch interval increasing unit equals to 1/N frame. N is a positive integer. The counting unit is coupled to the detection unit and configured to count frames according to a first refresh rate. The adjusting unit is coupled to the detection unit and the counting unit and configured to insert M frame porch interval increasing units every time when the counting unit counts L frames to adjust the first refresh rate to a second refresh rate, wherein the second refresh rate is lower than the first refresh rate. L and M are positive integers and L?M.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 25, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chun-Lin Hou, Shang-Ping Tang
  • Publication number: 20200111412
    Abstract: A display driving circuit applied to a display includes a detection unit, a counting unit and an adjusting unit. The detection unit is configured to detect N pulses of an emission control signal of the display in a frame and define a frame porch interval increasing unit accordingly. The frame porch interval increasing unit equals to 1/N frame. N is a positive integer. The counting unit is coupled to the detection unit and configured to count frames according to a first refresh rate. The adjusting unit is coupled to the detection unit and the counting unit and configured to insert M frame porch interval increasing units every time when the counting unit counts L frames to adjust the first refresh rate to a second refresh rate, wherein the second refresh rate is lower than the first refresh rate. L and M are positive integers and L?M.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 9, 2020
    Inventors: CHUN-LIN HOU, SHANG-PING TANG
  • Publication number: 20200091203
    Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.
    Type: Application
    Filed: April 12, 2019
    Publication date: March 19, 2020
    Inventors: Jinjin Xue, Dawei Shi, Feng Li, Lei Yao, Wentao Wang, Haifeng Xu, Lu Yang, Lin Hou, Jinfeng Wang, Mei Li, Yezhou Fang
  • Publication number: 20190244824
    Abstract: The present disclosure relates to an array substrate, a method for fabricating the same, a display panel, and a method for fabricating the same. The array substrate includes a substrate, an active layer on the substrate, a first insulating layer on the active layer, a gate electrode and a first electrode on the first insulating layer, wherein a projection of the first electrode on the substrate and a projection of the active layer on the substrate do not overlap, a third insulating layer on the first electrode, a projection of the third insulating layer on the substrate does not overlap with a projection of the active layer on the substrate, a second electrode on the third insulating layer, and a second insulating layer on the gate electrode and the second electrode.
    Type: Application
    Filed: October 9, 2018
    Publication date: August 8, 2019
    Inventors: Haifeng XU, Dawei SHI, Liman PENG, Wentao WANG, Lu YANG, Lei YAO, Jinfeng WANG, Lei YAN, Jinjin XUE, Lin HOU, Fang YAN, Xiaowen SI, Zhijin MAN, Yaoda HOU, Yi LI, Lizhen ZHAO, Lei WANG
  • Publication number: 20190165001
    Abstract: An array substrate, a method of manufacturing the same, and a display panel are provided, the array substrate includes a base substrate, and a pixel unit on the base substrate; and a reflective layer disposed on the base substrate and located in a portion of a region of the pixel unit, a surface of the reflective layer facing away from the base substrate includes a rugged structure.
    Type: Application
    Filed: June 19, 2018
    Publication date: May 30, 2019
    Inventors: Lei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Xiaowen Si, Fang Yan, Jinjin Xue, Lin Hou, Zhixuan Guo, Yuanbo Li, Xiaofang Li
  • Patent number: 10275978
    Abstract: A coin-operated washing/drying machine including a cabinet and a coin box assembly disposed within the cabinet. A supporting structure is fixedly disposed within the cabinet. At least a bottom surface of the coin box assembly is fixedly connected with the supporting structure by a fastener. The fastener passes through from the interior of the coin box assembly and is fixedly connected with the supporting structure. The supporting structure is disposed within the cabinet; the bottom surface of the coin box assembly is fixedly connected with the supporting structure; the fasteners such as screws are thus invisible from an overall appearance. Since the coin box assembly is fixed to the supporting structure by the bottom surface to cause such a fixing structure to be hidden in the bottom surface of the coin box assembly, thereby achieving a good anti-theft effect.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 30, 2019
    Assignee: QINGDAO HAIER WASHING MACHINE CO., LTD.
    Inventors: Kun Yang, Yiping Bian, Gongfa Ma, Bin Zhang, Lin Hou
  • Publication number: 20190072829
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, in which a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lei YAO, Dawei SHI, Wentao WANG, Lu YANG, Haifeng XU, Lei YAN, Jinfeng WANG, Xiaowen SI, Fang YAN, Jinjin XUE, Lin HOU, Yuanbo LI, Zhixuan GUO, Xiaofang LI
  • Publication number: 20180374416
    Abstract: A display driving apparatus applied to a panel. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 27, 2018
    Inventors: Chun-Lin HOU, Shao-Ping HUNG, Shang-Ping TANG