Patents by Inventor Lin LAI

Lin LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220406961
    Abstract: A micro light-emitting device has an epitaxial die having a top surface, a bottom surface and a plurality of sidewalls connected between the top surface and the bottom surface. A roughness of at least one part of the surface of at least one of the sidewalls is smaller than or equal to 10 nm, or an etch-pit density of the at least one part of the surface is smaller than 108/cm2, or a flatness tolerance of the at least one part of the surface is greater than 0.1 times a thickness of the epitaxial die. Therefore, the serious attenuation of the peak external quantum efficiency is prevented due to the sidewall damage effect after the light-emitting device is miniaturized.
    Type: Application
    Filed: November 1, 2021
    Publication date: December 22, 2022
    Inventors: Shen-Jie WANG, Yu-Yun LO, Yen-Lin LAI, Tzu-Yang LIN
  • Patent number: 11500801
    Abstract: A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: November 15, 2022
    Assignee: VIA Technologies Inc.
    Inventors: Yi-Lin Lai, Jiin Lai, Chin-Yin Tsai
  • Publication number: 20220360257
    Abstract: An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor.
    Type: Application
    Filed: August 24, 2021
    Publication date: November 10, 2022
    Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yi-Hsiang WANG, Wei-Lin LAI
  • Patent number: 11496944
    Abstract: A method for evaluation of UE route selection policy (URSP) rules is proposed. URSP is used by a UE to determine if a detected application can be associated to an established PDU session, can be offloaded to non-3GPP access outside a PDU session, or can trigger the establishment of a new PDU session. The UE first finds a non-default URSP rule with a matching traffic descriptor to the application. Then, the UE selects a route selection descriptor including a preferred access type from a list of RSDs of the non-default URSP rule. After that, the UE matches or establishes a Protocol Data Unit (PDU) session for the application by ignoring the preferred access type or using the preferred access type.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 8, 2022
    Assignee: MediaTek INC.
    Inventors: Chien-Chun Huang-Fu, Chia-Lin Lai
  • Patent number: 11495709
    Abstract: A patterned epitaxial substrate includes a substrate and a plurality of patterns. The substrate has a first zone and a second zone surrounding the first zone. The first zone is disposed around a center of the substrate. The patterns and the substrate are integrally formed, and the patterns are disposed on the substrate. The patterns include a plurality of first patterns and a plurality of second patterns. The first patterns are disposed in the first zone. The second patterns are disposed in the second zone. Sizes of the first patterns are different from sizes of the second patterns.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 8, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Kuang-Yuan Hsu, Chien-Chih Yen, Yen-Lin Lai, Shen-Jie Wang, Sheng-Yuan Sun
  • Publication number: 20220349047
    Abstract: A semiconductor wafer carrier structure includes a carrier body having a surface; a protective film covering the surface; a susceptor disposed on the carrier body; and a patterned coating film on the susceptor, wherein the patterned coating film has two or more different thicknesses, wherein patterns of the patterned coating film are symmetrically distributed with respect to a center of the susceptor.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 3, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Yen-Lin LAI, Jyun-De WU, Chi-Heng CHEN
  • Publication number: 20220349057
    Abstract: A semiconductor wafer carrier structure is provided. The semiconductor wafer carrier structure includes a susceptor and a patterned heat conduction part disposed on the susceptor. At least a portion of the patterned heat conduction part has a different heat conduction coefficient than the susceptor. A metal-organic chemical vapor deposition equipment is also provided. The metal-organic chemical vapor deposition equipment includes a carrier body having a plurality of carrier units. The above semiconductor wafer carrier structure is placed in at least one of the carrier units.
    Type: Application
    Filed: September 3, 2021
    Publication date: November 3, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Yen-Lin LAI, Jyun-De WU, Chi-Heng CHEN
  • Patent number: 11483754
    Abstract: A method of handling multi-access (MA) Protocol data unit (PDU) session handover is proposed. A UE and network can support Access Traffic Steering Switching and Splitting (ATSSS) functionalities to distribute traffic over 3GPP access and non-3GPP access for the established MA PDU session. An ATSSS-Supported UE first establishes a MA PDU Session on both 3GPP and non-3GPP access in a currently registered PLMN which is an ATSSS-Supported network. The UE then moves from the ATSSS-Supported network to an ATSSS-not-Supported network and finally reaches another ATSSS-Supported network. In one novel aspect, a solution is provided on how to handle the ongoing MA PDU Session with two accesses under handover scenarios between ATSSS-Supported and ATSSS-not-Supported networks. Furthermore, if the ongoing MA PDU Session cannot handover, a solution is provided on how to handle the MA PDU Session.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: October 25, 2022
    Assignee: MediaTek INC.
    Inventors: Chia-Lin Lai, Chien-Chun Huang-Fu
  • Patent number: 11456590
    Abstract: A short circuit detection module includes a power unit including a battery for providing a voltage of the battery, a monitoring unit, a switch unit, a heating unit and a control unit. The monitoring unit is connected with the power unit. The switch unit includes a first MOSFET, the monitoring unit is connected with the source electrode of the first MOSFET. The heating unit is connected with the drain electrode of the first MOSFET, the drain electrode of the first MOSFET transmits a heating current to the heating unit. A heating voltage is generated at an output terminal of the short circuit detection module. The control unit is connected with and controls the power unit, the monitoring unit, the switch unit and the heating unit. When the heating voltage is greater than a critical value of the heating voltage, the control unit turns off the first MOSFET.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 27, 2022
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventors: Chin Huang Tseng, Wen Bing Hsu, Hui Lin Lai
  • Publication number: 20220286850
    Abstract: A method of handling authentication reject upon accessing an SNPN using credentials from a credential holder is proposed. A UE is configured with a “list of subscriber data”. The UE selects an SNPN using the configured list of subscriber data, e.g., based on the SNPN selection parameters contained in a selected entry of the list of subscriber data. Based on the selected entry, the UE selects an SNPN, and then tries to access the selected SNPN using credentials supplied by a subscribed SNPN. When UE receives an authentication reject message from the network, UE considers that the selected entry of the list of subscriber data is invalid. However, other entries related to the current selected SNPN are still valid. UE is still able to access the current selected SNPN, using credentials supplied in another entry of the list of subscriber data.
    Type: Application
    Filed: February 10, 2022
    Publication date: September 8, 2022
    Inventors: Yuan-Chieh Lin, Chia-Lin Lai
  • Publication number: 20220285423
    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 8, 2022
    Inventors: Tsang-Yu LIU, Shu-Ming CHANG, Chaung-Lin LAI
  • Publication number: 20220240210
    Abstract: A method to facilitate onboarding registration via an onboarding network (ON) that is a stand-alone non-public network (ON-SNPN) is proposed. A UE is preconfigured with default UE credentials for Onboarding. UE discovers and selects an ON-SNPN and registers to the ON-SNPN using default UE credentials. Both user plane (UP) and control plane (CP) provisioning procedure can be used to obtain the SNPN credentials from a subscriber owner (SO) via an ON-SNPN access connectivity. In accordance with one novel aspect, when UE sends a registration request for UE onboarding registration, the registration request comprises information for registration type (e.g., SNPN ONBOARDING), and UE supported provisioning procedure (e.g., CP, UP, or both). Upon successful registration, UE follows the supported provisioning procedure (i.e., CP or UP) decided by the ON-SNPN to obtain the SNPN credentials from the SO-SNPN via the ON-SNPN access connectivity to a Provisioning Server (PVS).
    Type: Application
    Filed: December 22, 2021
    Publication date: July 28, 2022
    Inventors: Chia-Lin Lai, Yuan-Chieh Lin, Chien-Chun Huang-Fu, Guillaume Sebire, Marko Niemi
  • Publication number: 20220232506
    Abstract: A method supporting enhanced network identity (NID) provisioning under User Equipment (UE) mobility scenarios between different types of networks is proposed. When a UE registers to an SNPN, the UE is assigned with a 5G-GUTI by the SNPN. The SNPN is identified by an SNPN ID==PLMN ID+NID. When the UE moves from the SNPN to another target network having a target AMF, the UE triggers a mobility registration update procedure and provides the 5G-GUTI along with NID information in a Registration Request to the target AMF. The target AMF can use the NID information along with the 5G-GUTI to find a source AMF for deriving UE context for the subsequent operations during the mobility registration update procedure. Providing NID information along with 5G-GUTI can assist the target AMF to find the source AMF efficiently, preventing a potential registration procedure failure.
    Type: Application
    Filed: December 21, 2021
    Publication date: July 21, 2022
    Inventors: Chia-Lin Lai, Yuan-Chieh Lin
  • Publication number: 20220219970
    Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Tsang-Yu LIU, Chaung-Lin LAI, Shu-Ming CHANG
  • Publication number: 20220171543
    Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.
    Type: Application
    Filed: November 17, 2021
    Publication date: June 2, 2022
    Inventors: Kim Soon Jway, Shu-Lin Lai, Yi-Ping Kuo
  • Publication number: 20220172327
    Abstract: A method for correcting abnormal point cloud is disclosed. Firstly, receiving a Primitive Point Cloud Data set by an operation unit for dividing a point cloud array into a plurality of sub-point cloud sets and obtaining a plurality of corresponding distribution feature data according to an original vector data of the Primitive Point Cloud Data set. Furthermore, recognizing the sub-point cloud sets according to the corresponding distribution feature data for correcting recognized abnormal point cloud. Thus, when the point cloud array is rendered to a corresponding image, the color defect of the point cloud array will be improved or decreased for obtaining lossless of the corresponding image.
    Type: Application
    Filed: June 22, 2021
    Publication date: June 2, 2022
    Inventors: CHIH-WEI WANG, CHUAN-LIN LAI, CHIA-CHEN KUO, I-CHEN WU
  • Patent number: 11334429
    Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 17, 2022
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen, Ying-Che Chung
  • Patent number: 11329192
    Abstract: The embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure also includes a first buffer layer disposed on the substrate. The semiconductor structure further includes a second buffer layer disposed on the first buffer layer. The semiconductor structure includes a semiconductor-based layer disposed on the second buffer layer. The second buffer layer includes aluminum, and the aluminum content of the second buffer layer gradually increases in the direction away from the substrate.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: May 10, 2022
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Hsin-Chiao Fang, Shen-Jie Wang, Yen-Lin Lai
  • Patent number: 11319208
    Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 3, 2022
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
  • Publication number: 20220124497
    Abstract: A method of enhanced handling of a Forbidden SNPN list by a UE is proposed. When the UE registers to a first SNPN using credentials supplied by a second SNPN and receives a rejection from the network, the UE adds an entry of the first SNPN into one of the forbidden SNPN lists, and also creates an association between the first SNPN and the second SNPN. As a result, the UE is refrained from registering to the first SNPN using the credentials supplied by the second SNPN as long as the first SNPN entry remains in the forbidden SNPN list. However, the UE is allowed to register to the first SNPN using credentials supplied by other SNPNs.
    Type: Application
    Filed: September 14, 2021
    Publication date: April 21, 2022
    Inventors: Yuan-Chieh Lin, Chien-Chun Huang-Fu, Chia-Lin Lai