Patents by Inventor Lin Liu

Lin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12082576
    Abstract: A DSC (Differential Scanning calorimetry) electrode system capable of applying an electric field includes a differential scanning calorimeter, a computer, a signal generator, a self-pressurization liquid nitrogen tank and a reference crucible, wherein the self-pressurization liquid nitrogen tank is connected to the differential scanning calorimeter and used for controlling temperature in real time; the differential scanning calorimeter is connected to the computer and used for transmitting signals and recording experiment results. The DSC electrode system also includes a microelectrode crucible that includes a ceramic crucible, a ceramic crucible cover, welding spots, two electrodes and electrode wires, wherein the two electrodes are respectively fixed in the ceramic crucible; a gap is reserved between the electrodes and used for storing a tested sample; the welding spots are reserved at upper ends of the electrodes.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 10, 2024
    Assignee: XI'AN JIAOTONG UNIVERSITY
    Inventors: Lisheng Zhong, Xiaoyuan Song, Jinghui Gao, Qinxue Yu, Lin Liu, Jiaxi He, Yafei Li
  • Publication number: 20240295714
    Abstract: An optical lens is provided, including one first lens sheet having a first optical zone and a first structural zone; a second lens component, including a second lens barrel and at least one second lens sheet mounted in the second lens barrel, the second lens sheet has a second optical zone and a second structural zone, the second structural zone and the second lens barrel constitute a structural zone of the second lens component, and there is a first gap between a top surface of the structural zone and a bottom surface of the first structural zone; and a first glue material, located in the first gap. The first glue material extends outwardly along the top surface of the structural zone of the second lens component and covers at least a part of an outer lateral side surface of the first structural zone.
    Type: Application
    Filed: May 10, 2024
    Publication date: September 5, 2024
    Applicant: NINGBO SUNNY OPOTECH CO., LTD.
    Inventors: Yinli FANG, Heng JIANG, Takehiko TANAKA, Lin LIU, Shuijia CHU
  • Publication number: 20240297639
    Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
    Type: Application
    Filed: April 25, 2024
    Publication date: September 5, 2024
    Inventors: Po-Chia LAI, Meng-Hung SHEN, Chi-Lin LIU, Stefan RUSU, Yan-Hao CHEN, Jerry Chang-Jui KAO
  • Patent number: 12073162
    Abstract: A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheok-Kei Lei, Jerry Chang Jui Kao, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chien-Hsing Li
  • Patent number: 12074603
    Abstract: The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Jheng Ou-Yang, Chi-Lin Liu, Shang-Chih Hsieh, Wei-Hsiang Ma, Kai-Chi Huang
  • Patent number: 12068747
    Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Lin Liu, Bei-Shing Lien, Yi-Wen Chen, Chin-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Publication number: 20240274495
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in a packaging layer, and a circuit structure is formed on the packaging layer and electrically connected to the first electronic element and the second electronic element, where the circuit structure has a heat dissipation portion thermally connected to the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation portion, so as to avoid the problem of affecting the operation of the second electronic element due to overheating of the packaging layer.
    Type: Application
    Filed: June 30, 2023
    Publication date: August 15, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shuai-Lin LIU, Nai-Hao KAO, Yu-Po WANG
  • Publication number: 20240274505
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in an encapsulation layer, and a circuit structure is disposed on the encapsulation layer and electrically connected to the first electronic element and the second electronic element. The circuit structure has a hollow area corresponding to the first electronic element, and a heat dissipation structure is disposed in the hollow area to thermally connect the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation structure, so as to avoid the problem of affecting the operation of the second electronic element due to the overheating of the encapsulation layer.
    Type: Application
    Filed: June 6, 2023
    Publication date: August 15, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shuai-Lin LIU, Nai-Hao KAO, Yu-Po WANG
  • Publication number: 20240275384
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: GREG GRUBER, CHI-LIN LIU, MING-CHANG KUO, LEE-CHUNG LU, SHANG-CHIH HSIEH
  • Publication number: 20240266210
    Abstract: The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer, and a metal layer is filled in the compensation groove.
    Type: Application
    Filed: March 1, 2023
    Publication date: August 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chien Chung, Yu-Chin Huang, Chao-You Hung, Wei-Lin Liu
  • Publication number: 20240266247
    Abstract: An IC device includes a heat transfer structure electrically isolated from a resistor. The resistor includes first and second metal segments extending in a first direction in a first metal layer and a third metal segment extending perpendicular to the first direction in a second metal layer below the first metal layer, the third metal segment electrically connecting the first and second metal segments to each other. The heat transfer structure includes fourth and fifth metal segments extending in the first direction in the first metal layer adjacent to the first and second metal segments, sixth and seventh metal segments extending in the second direction in the second metal layer, each of the sixth and seventh metal segments electrically connecting the fourth and fifth metal segments to each other, and a thermally conductive path extending from the sixth or seventh metal segment to an underlying active area.
    Type: Application
    Filed: March 25, 2024
    Publication date: August 8, 2024
    Inventors: Jaw-Juinn HORNG, Szu-Lin LIU, Wei-Lin LAI
  • Patent number: 12054060
    Abstract: A charging connector for an electrical vehicle has a connector base, a tubular first conductive terminal mounted in the connector base, an insulating isolation member mounted in the first conductive terminal, and a second conductive terminal mounted in a center of the isolation member and coaxially disposed in and electrically isolated from the first conductive terminal. The isolation member has at least one annular groove recessed in an upper surface of the isolation member, extending downwardly, and coaxially surrounding the second conductive terminal. A creepage distance between the first conductive terminal and the second conductive terminal is increased and a surface area for heat dissipation is increased to meet safety specifications.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: August 6, 2024
    Assignee: T-Conn Precision (Zhongshan) Co., Ltd.
    Inventors: Jia-Heng Zheng, Wu-Lin Liu
  • Patent number: 12055783
    Abstract: The present application provides an optical lens, comprising: a first lens component comprising at least one first lens sheet; a second lens component comprising a second lens barrel and at least one second lens sheet mounted in the second lens barrel, wherein the at least one second lens sheet and the at least one first lens sheet together constitute an imageable optical system, wherein at least a part of the outer side surface of the second lens sheet at the bottommost end among the at least one second lens sheet is exposed to the outside of the second lens barrel, and the top surface of the second lens sheet at the bottommost end bears against the bottom surface of the second lens barrel; and a connecting medium adapted to fix the first lens component and the second lens component together. The present application further provides a corresponding camera module and optical lens and camera module assembly methods.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 6, 2024
    Assignee: NINGBO SUNNY OPOTECH CO., LTD
    Inventors: Yinli Fang, Heng Jiang, Takehiko Tanaka, Lin Liu, Shuijia Chu
  • Patent number: 12055786
    Abstract: A lens group assembly includes a lens barrel and a plurality of lenses. The lenses are embedded in the lens barrel to assemble the lens group, and there is an adhesive material between at least two of the lenses and/or between at least one of the lenses and the lens barrel to reinforce the structural strength of the assembled lens group. A corresponding optical lens, a camera module and a lens group assembling method are also included. Assembling accuracy and assembling stability of the high-sensitivity multi-lens optical system is improved by increasing the adhesion between the lenses. Variation of the optical lens is reduced based on an active calibration process. Adhesive material that might otherwise overflow is accommodated. Defects caused by the assembly of the optical lens are reduced based on the active calibration process, especially the field curvature and peak variation.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 6, 2024
    Assignee: NINGBO SUNNY OPOTECH CO., LTD.
    Inventors: Takehiko Tanaka, Heng Jiang, Lin Liu, Liefeng Chen
  • Publication number: 20240255977
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Application
    Filed: April 11, 2024
    Publication date: August 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng CHEN, Yen-Lin LIU, Chia-Wei HSU, Jo-Yu WU, CHANG-FEN HU, Shao-Yu LI, Bo-Ting CHEN
  • Patent number: 12052534
    Abstract: The present invention provides a heat dissipation device having a speaker box, a heating element and a heat conductor. The speaker box includes a housing having a sound outlet hole and a metal embedding member embedded in the housing. The speaker unit includes a diaphragm. The heat conductor is connected to the heating element. In the present invention, the heat conductor transfers the heat generated by the heating element to the metal embedding member, the metal embedding member conducts heat to the outside of the sound outlet hole through the air in the front cavity.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 30, 2024
    Assignee: AAC TECHNOLOGIES PTE. LTD.
    Inventors: Xingzhi Huang, Lin Liu, Dijiang Tong, Zhe Zhang, Jun Wu, Zhichen Chen, Zhaoyu Yin
  • Publication number: 20240249991
    Abstract: A semiconductor structure includes a substrate having a front side and a back side, one or more dielectric layers over the front side, and a conductive structure. The one or more dielectric layers include a thermal sensor region and two dummy regions sandwiching the thermal sensor region along a second direction from a top view. The thermal sensor region and the two dummy regions extend longitudinally along a first direction generally perpendicular to the second direction from the top view. The conductive structure is embedded in the thermal sensor region of the one or more dielectric layers. The conductive structure includes conductive lines parallel to each other and extending longitudinally along the first direction, and conductive bars and vias electrically connecting the conductive lines. The conductive lines in a same dielectric layer of the one or more dielectric layers are electrically connected one by one zigzaggedly from the top view.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 25, 2024
    Inventors: Yu-Hsiang Chen, Hsiu-Wen Hsueh, Szu-Lin Liu, Wen-Sheh Huang, Chloe Hsin-Yi Chen, Wei-Lin Lai
  • Patent number: 12042997
    Abstract: An automatic leveling device of a 3D printer, and a 3D printer is provided. The automatic leveling device includes a photoelectric switch, an electromagnetic assembly and a probe assembly. The photoelectric switch is arranged in a housing and defines a photosensitive groove. The electromagnetic assembly is arranged in the housing and defines a sliding hole. The probe assembly is slidably engaged in the sliding hole, and an end of the probe assembly is engaged in the photosensitive groove. The electromagnetic assembly is capable of driving the probe assembly to make the end of the probe assembly move out of the photosensitive groove. The automatic leveling device has the advantages of simple structure, low manufacturing difficulty, low production cost, simple and stable leveling mode, high detection repetition accuracy and no complex circuit and software cooperation.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: July 23, 2024
    Assignee: Shenzhen Creality 3D Technology Co., Ltd.
    Inventors: Hui-Lin Liu, Jing-Ke Tang, Chun Chen, Dan-Jun Ao, Peng-Jian Li, Bin Qiao, Pin Chen
  • Patent number: 12046851
    Abstract: An assembled electrical connector has a base having a terminal stage formed on a top thereof, an upper cap, a first conductive terminal mounted in a center of the terminal stage, and a second conductive terminal externally assembled on the base. The second conductive terminal is a ring sheet, surrounds the terminal stage, and is electrically isolated from the first conductive terminal via the terminal stage. The upper cap is tubular and is connected on the top of the base. The second conductive terminal abuts against an internal surface of the upper cap. Because the second conductive terminal is externally assembled on the terminal stage of the base and is not combined with the base via insert molding, the second conductive terminal does not need to use a machining product.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: July 23, 2024
    Assignee: T-Conn Precision (Zhongshan) Co., Ltd.
    Inventors: Jia-Heng Zheng, Wu-Lin Liu
  • Patent number: D1040838
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: September 3, 2024
    Assignee: Aristocrat Technologies Australia Pty Limited
    Inventors: Antoon Visser, Lin Liu, Lauren Paterson, Benjamin Tinworth