Abstract: The invention provides a resin composition that may effectively increase glass transition temperature while maintaining low-k electrical specification. The resin composition includes a first resin polymerized by a monomer mixture including styrene, divinylbenzene, and ethylene, a second resin including a bismaleimide-modified polyphenylene ether resin, a divinylbenzene crosslinking agent, a halogen-free flame retardant, a spherical silica, and a siloxane coupling agent.

Abstract: A nano-delivery carrier for targeted tumor administration and an application thereof are provided, which relate to the technical field of targeted anti-tumor dugs. A preparation method of the nano-delivery carrier for targeted tumor administration includes: mixing a NucA targeting a tumor and DSPE-PEG2000-NHS with DMF to obtain a mixture, adding triethylamine into the mixture, adjusting a pH of the mixture added with the triethylamine to 8-9 to react at room temperature, to thereby obtain the nano-delivery carrier for targeted tumor administration. An anti-tumor drug based on the nano-delivery carrier can correctly target to the tumor to be killed, for example, an anti-tumor drug based on the nano-delivery carrier and including RVT can target and kill ovarian cancer cells without damaging normal tissues.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: This disclosure provides a wafer processing method having the following steps: providing a wafer (10), an immersion device (100), a carrier (200), and a spray device (300); turning the wafer (10) from a horizontal manner to an upright manner; upright placing the wafer (10) into the immersion device (100) for immersion; taking the wafer (10) out from the immersion device (100) and placing that onto the carrier (200) horizontally; spraying a liquid on the wafer (10) by the spray device (300); rinsing the wafer (10); rotating the carrier (200) to dry the wafer (10). Multiple steps for processing the wafer (10) may be performed on the same carrier (200) to accelerate the process.

Abstract: A liquid cooling device comprises a cabinet, a liquid flowing unit, a liquid tray, and a liquid sensor. The cabinet is configured for containing an electronic component. The liquid flowing unit comprises a plurality of liquid delivery pieces connected and configured for circulating coolant to cool the electronic component. The liquid tray defines a confluence groove configured for gathering the coolant leaking from two connected ones of the plurality of liquid delivery pieces. The liquid sensor is placed in the confluence groove and is configured for sending a signal when contacting with the coolant. When the coolant leaks from two connected ones of the plurality of liquid delivery pieces then drops on the liquid tray and flows into the confluence groove by gravity, the liquid sensor contacts with the coolant in the confluence groove and sends the signal. A server with the liquid cooling device is also disclosed.

Abstract: An integrated circuit includes a first conducting line and a second conducting line in a first metal layer above a first transistor and a second transistor. The first conducting line and the second conducting line, which are parallel and adjacent to each other, form a metal-insulator-metal capacitor. Each of the first transistor and the second transistor forms a metal-insulator-semiconductor capacitor. The circuit also includes a third conducting line connected to a source and a drain of the first transistor and configured to receive a first reference voltage. The circuit still includes a fourth conducting line connected to a source and a drain of the second transistor and configured to receive a second reference voltage.

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Abstract: Disclosed herein are oligosaccharides and intermediates useful for the production thereof. The compounds are useful as analytical standards and as intermediates for the preparation of more complex oligosaccharide and N-glycan products. The compounds may be prepared in high purity using the selective stop/go synthetic methods disclosed herein.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: An immersion cooling device includes a box body containing coolant, a heat-generating component received in the box body and immersed in the coolant, a slide rail received in the box body, fixed to the box body and located above the coolant, a condenser slidably disposed on the slid rail, a cover body adapted to cover the box body and to be opened relative to the box body, and an inlet pipe connected to the condenser and passing through and sealed from the cover body.

Abstract: An immersion cooling device includes a housing defining a receiving chamber, a working liquid received in the receiving chamber, a condenser received in the receiving chamber and located outside the working liquid, and a blocking member received in the receiving chamber. The blocking member includes a plurality of blocking bodies dispersed on a top surface of the working liquid.

Abstract: An immersion cooling device includes a housing defining a chamber, a working liquid received in the chamber, a condenser received in the chamber and located outside the working liquid, and at least one support plate received in the chamber. Each of the at least one support plate includes a first portion and a second portion connected to the first portion. The first portion is immersed in the working liquid and configured to hold an electronic device. The second portion protrudes from the working liquid. The second portion defines a slot extending through the second portion, and an opening of the slot faces the condenser.

Abstract: The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.

Abstract: An optical system and the adjusting device thereof. The optical system includes an optical device. The adjusting device is configured for adjusting a location of a center of the optical device. The adjusting device includes a first adjusting element which is movable along a first axis and is propped against the optical device, a second adjusting element which is movable along a second axis and is propped against the optical device, and a third adjusting element which is movable along a third axis and is propped against the optical device. The center of the optical device is spaced apart from where the first axis and the second axis meet and/or where the first axis and the third axis meet.

Abstract: A bridge device for bridging a host device and a data storage device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface. The second transmission interface is coupled to the first transmission interface through a bus. The first transmission interface operates in a slave mode and the second transmission interface operates in a master mode. The first transmission interface and the second transmission interface generate multiple transfer data chunks in compliance with a common bridge transfer format to perform transfer operations in dual directions for respectively transferring a command and data between a host device and a data storage device.

Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.

Abstract: A method of information processing includes displaying a running screen of a target virtual game in a first time unit, the target virtual game includes at least a first virtual character that is manipulated by an artificial intelligence (AI) object. The method also includes obtaining battle reference data associated with the running screen, the battle reference data includes battle data fed back by the first virtual character when the first virtual character participates in the target virtual game in the first time unit. The method also includes displaying execution prediction information of at least a to-be-executed candidate operation based on the battle reference data. Apparatus and non-transitory computer-readable storage medium counterpart embodiments are also contemplated.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor, a first pull-up transistor and an output circuit. The input circuit is coupled to a first and second node, and is configured to receive a first and second enable signal, and to set a first control signal of the first node responsive to the first or second enable signal. The cross-coupled pair of transistors is coupled between the first and second node. The first pull-up transistor includes a first gate terminal configured to receive a clock input signal, a first drain terminal coupled to the second node, and a first source terminal coupled to a voltage supply. The output circuit is coupled between the second node and an output node, and configured to output an output clock signal responsive to the second control signal.