Abstract: This application discloses an application information display method and a related device. The method includes: An electronic device detects an update event of application information of a first application, and in response to the update event, the electronic device determines whether the first application is locked by an application lock, where the application information may be a widget or a notification message; and the electronic device displays a locking view over the application message after determining that the first application is locked by the application lock.

Abstract: A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.

Abstract: The disclosure provides a resin composition, a substrate, and a copper clad laminate, wherein the resin composition includes a naphthalene ring epoxy resin, a bismaleimide resin, a crosslinking agent, polysiloxane, an accelerator, and a filler.

Abstract: This invention generally relates to a novel induced cytoplasmic IVT (ICIVT) composition useful for inducing in-vitro transcription (IVT)-like RNA/mRNA amplification in the cells of interest after transfection in vitro, ex vivo and/or in vivo. The present invention is useful for designing and developing a variety of RNA/mRNA medicines as well as vaccines comprising a mixture of at least a promoter-linked RNA/mRNA-coding DNA (PLRcD) template and another DNA-dependent RNA polymerase (DdRP) mRNA sequence. Preferably, the DdRP mRNA may be selected from the mRNA of T7, T3 and/or SP6 RNA polymerase, or a combination thereof, while the PLRCD template may encode the transcripts of antisense RNA oligonucleotide (aRNA-ASO), small interferring RNA (siRNA), double-stranded RNA (dsRNA), short hairpin RNA (shRNA), microRNA (miRNA)/microRNA precursor (pre-miRNA), long noncoding RNA (lncRNA), messenger RNA (mRNA), and/or self-amplifying RNA/mRNA (saRNA/samRNA), or a combination thereof.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: The present disclosure provides an adapter bracket, which includes a first portion, a second portion and a third portion. The first portion includes a protruding portion extending from a first bottom surface of the first portion in a direction perpendicular to the first bottom surface. The second portion, has an elevation with respect to the first bottom surface of the first portion. The second portion comprising a first hole. The third portion extends between the first portion and the second portion.

Abstract: An integrated circuit includes a first temperature-sensitive device having a first stacked gate device formed and a second stacked gate device, and a second temperature-sensitive device having a third stacked gate device. The first temperature-sensitive device is configured to generate a first voltage which monotonically increases with an absolute temperature. The second temperature-sensitive device is configured to generate a second voltage which monotonically decreases with the absolute temperature. The integrated circuit also includes an output terminal configured to generate a reference voltage which is based on the first voltage from the first temperature-sensitive device and the second voltage from the second temperature-sensitive device. Each of the first stacked gate device, the second stacked gate device, and the third stacked gate device is formed with a first group of field-effect transistors stacked together.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a first optoelectronic element having a first optical fiber connection portion is disposed on an electronic module, a second optoelectronic element having a second optical fiber connection portion is disposed on a first level layer of a lower carrying portion of a step-shaped carrier structure, and the electronic module is disposed on a second level layer of the step-shaped carrier structure and the second optoelectronic element having the second optical fiber connection portion, so that the electronic module is electrically connected to the second optoelectronic element having the second optical fiber connection portion. Thereby, two optoelectronic elements having optical fiber connection portions can be easily and vertically integrated, and the second optoelectronic element can be stably carried by the step-shaped carrier structure.

Abstract: The present disclosure provides a resistive device. The resistive device includes a conductive structure, a row of first vias, and a row of second vias. The conductive structure has a first side and a second side opposite to the first side, and a first surface connected between the first side and the second side. The row of first vias extends through the conductive structure in a first direction substantially perpendicular to the first surface. The row of first vias is closer to the first side than the second side. The row of second vias extends through the conductive structure in the first direction. The row of second vias is disposed between the first side of the conductive structure and the row of first vias.

Abstract: A system, device and method are provided for ingesting data onto cloud computing environments. The illustrative method includes providing an accelerator in a cloud computing environment for ingestion of data into the cloud computing environment. The method includes automatically, with the accelerator (1) verifying that one or more templates defining ingestion parameters are populated on the cloud computing environment, (2) verifying that resources in a target destination in the cloud computing environment have been provisioned, (3) populating, based on the one or more templates, and with a pipeline of tasks, one or more configuration reference destinations for transforming raw data into a format compatible with the provisioned target destination. The method includes ingesting a data file into the verified target destination in the cloud computing environment based on the verified one or more templates and populated configuration reference destinations.

Abstract: An overlay mark includes a previous layer mark and a current layer mark. The previous layer mark includes a plurality of first work zones. Each first working zone includes a first sub-region and a second sub-region, wherein the first sub-region is closer to a center point of the previous layer mark than the second sub-region. The previous layer mark includes a first mark and an auxiliary mark respectively in the first sub-region and the second sub-region of each first working zone. The current layer mark includes a plurality of second working zones. Each second working zone includes a first sub-region and a second sub-region. The current layer mark includes a second mark disposed in the second sub-region of each second working zone. The overlay mark may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.

Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.

Abstract: A computing system includes a computing tray for receiving a computing device; a latch attached to the computing tray for releasing the computing tray during installation or removal operations; and a lock assembly for preventing accidental release of the computing tray. The lock assembly includes a fixed bracket having two fixed sides, one of the fixed sides being a mounting side attached to the computing tray near the latch; and a movable bracket having two movable sides attached respectively to the two fixed sides. The movable bracket is adjustable relative to the fixed bracket between a releasing position and a secured position. The movable bracket allows the latch to release the computing tray in the releasing position, and the movable bracket physically blocks the latch from releasing the computing tray in the secured position.

Abstract: Disclosed is a resin composition including a resin. The resin includes a benzoxazine resin, an epoxy resin, and a modified maleimide resin. The modified maleimide resin is formed from a dicyclopentadiene (DCPD)-based resin having an amino group and a maleic anhydride by a condensation polymerization. The dicyclopentadiene-based resin having an amino group is formed by performing a nitration and a hydrogenation to a dicyclopentadiene phenolic resin.

Abstract: A bidirectional Littrow two-degree-of-freedom grating interference measurement device based on double gratings includes a transmission two-dimensional grating and a reflection two-dimensional grating. A dual-frequency laser emitted by a light source passes through the transmission two-dimensional grating with a specific grating pitch to form four beams in X direction and Y direction, the four beams are incident on the reflection two-dimensional grating at a Littrow angle, and the four beams diffracted by the reflection two-dimensional grating return to the transmission two-dimensional grating in an incidence direction along the same path; different orders of transmission light of the four beams of light in different directions may form stable interference signals carrying displacement information, and the stable interference signals are received by a detector.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A heterojunction battery and a preparation method therefor are provided. The heterojunction battery includes a crystalline silicon layer, a first intrinsic amorphous silicon layer, an N-type doped microcrystalline silicon layer, a first transparent conductive layer, and a first metal electrode are sequentially arranged on a front surface of the crystalline silicon layer from inside to outside, and a second intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer, a second transparent conductive layer, and a second metal electrode are sequentially arranged on a back surface of the crystalline silicon layer from inside to outside. A local reduction layer is formed on a surface of the first transparent conductive layer that is under the first metal electrode and/or on a surface of the second transparent conductive layer that is under the second metal electrode.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.