Patents by Inventor Lin Lu

Lin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153708
    Abstract: A wound capacitor package structure includes a wound assembly, a conductive assembly, a package assembly, a bottom seat plate and a pin protection assembly. The conductive assembly includes a first and a second conductive pin. The package assembly is configured for enclosing the wound assembly. The bottom seat plate is disposed on a bottom side of the package assembly. The pin protection assembly includes a first pin protection layer configured to partially cover the first conductive pin, and a second pin protection layer configured to partially cover the second conductive pin. The first conductive pin includes a first exposed portion exposed outside the package assembly, and the second conductive pin includes a second exposed portion exposed outside the package assembly. The first and the second pin protection layer are disposed on the first and the second exposed portion for protecting the first and the second conductive pin, respectively.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 9, 2024
    Inventors: CHIEH LIN, CHUNG-JUI SU, CHENG-HAO LU
  • Publication number: 20240143887
    Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: CHI-TA LU, CHIA-HUI LIAO, YIHUNG LIN, CHI-MING TSAI
  • Publication number: 20240145903
    Abstract: Base station antennas are provided. A base station antenna includes a reflector that has a plurality of faces that face in different directions. The base station antenna includes a plurality of arrays of radiating elements that are on the faces, respectively, of the reflector. Moreover, the base station antenna includes a plurality of parasitic elements that are on the faces. Related methods of operating a base station antenna are also provided.
    Type: Application
    Filed: June 28, 2023
    Publication date: May 2, 2024
    Inventors: Lin Wang, Jianpeng Lu, Haiyan Chen, Hangsheng Wen
  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Patent number: 11972975
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
  • Patent number: 11972972
    Abstract: A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 30, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Mu-Lin Li
  • Publication number: 20240133173
    Abstract: The present disclosure relates to a fabricated concrete connection structure and a construction method, the structure including shear wall members. Tops of the shear wall members are fixedly connected to a plurality of connection female heads, and the plurality of connection female heads are arranged at equal intervals along length directions of the shear wall members. Reinforcing cage pre-formed holes penetrate through the tops and bottoms of the shear wall members. A plurality of connection male heads are arranged at equal intervals along the length directions of the shear wall members, and the plurality of connection male heads are in one-to-one correspondence with the plurality of connection female heads. One sides of the bottoms of the shear wall members are fixedly connected to folding plates. The present disclosure can achieve the purpose of connecting the shear wall members conveniently and quickly, improving the efficiency and quality of construction.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 25, 2024
    Inventors: Bo Liu, Juannong Chen, Lin Gao, Yankai Lu
  • Publication number: 20240135793
    Abstract: The present disclosure discloses an acousto-magnetic (AM) anti-theft marker and use thereof. The AM anti-theft marker includes at least one resonator(s), where when the resonator(s) does not include cobalt, a weight percentage of nickel is 0 wt % to 39 wt %; or when the resonator(s) includes cobalt, a total weight percentage of nickel and cobalt is higher than 0 wt % and no more than 36 wt %. Although this AM anti-theft marker's resonator(s) of the present disclosure does not include or only includes a very small amount of nickel and cobalt, it still has good alarm performance; and the existing detectors can effectively detect the AM anti-theft marker of the present disclosure within a predetermined security alarming distance. It can be seen that this AM anti-theft marker has a commercial value, and can reduce the loss prevention cost of business and the consumption of earth resources.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Inventors: Lin Li, Caishan Lu, Caobin LIU
  • Patent number: 11965833
    Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.
    Type: Grant
    Filed: November 26, 2020
    Date of Patent: April 23, 2024
    Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jing-Zhi Hou, Lin-Hui Cheng, Yan-Chao Ma, Jin-Cai Zhou, Zi-Long Ma, Neng-Neng Zhang, Yi Chen, Chen-Xi Tang, Meng Lu, Peng Zhou, Ling-Hui Zhang, Lu-Hui Fan, Shi-Gang Xu, Cheng-Yi Chao, Liang-Yi Lu
  • Patent number: 11967558
    Abstract: A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 23, 2024
    Assignees: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu, Jium-Ming Lin
  • Patent number: 11965037
    Abstract: Provided is an anti-HER3 humanized monoclonal antibody. The antibody binds HER3 antigen, has high affinity and biological activity and low immunogenicity, and is stable in structure. The antibody can be used for preparing drugs for preventing or treating HER3-related diseases.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: April 23, 2024
    Assignee: SHANGHAI INSTITUTE OF BIOLOGICAL PRODUCTS CO., LTD.
    Inventors: Aidong Qu, Hongyuan Liang, Fanhong Xu, Aoxiang Li, Lina Wu, Jingye Zhu, Jianhua Qiu, Jin Lu, Lin Zhang, Xin Zhao, Xiaofei Song
  • Publication number: 20240130022
    Abstract: This application relates to the field of lighting, and discloses an LED filament. The LED filament includes an LED chip unit, a light conversion layer, and an electrode. The light conversion layer covers the LED chip unit and part of the electrode, and a color of a light emitted by the LED filament after lighting is different from a color of the light conversion layer. This application has the characteristics of uniform light emission and good heat dissipation effect.
    Type: Application
    Filed: September 18, 2022
    Publication date: April 18, 2024
    Inventors: Tao Jiang, Lin Zhou, Ming-Bin Wang, Chih-Shan Yu, Rong-Huan Yang, Ji-Feng Xu, Heng Zhao, Jian Lu, Qi Wu
  • Publication number: 20240129860
    Abstract: Techniques and apparatus for configurable radio frequency (RF) exposure compliance based on region. An example method of wireless communication by a user equipment (UE) generally includes identifying a region in which the UE is located, selecting at least one of a mode or one or more parameters for RF exposure compliance based on the identified region, and transmitting a signal at a transmission power level based at least in part on the at least one of the selected mode or the selected one or more parameters.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 18, 2024
    Inventors: Lin LU, Jagadish NADAKUDUTI, Akhil DEODHAR, Troy CURTISS, Paul GUCKIAN
  • Patent number: 11961912
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Patent number: 11952768
    Abstract: The present disclosure relates to a fabricated concrete connection structure and a construction method, the structure including shear wall members. Tops of the shear wall members are fixedly connected to a plurality of connection female heads, and the plurality of connection female heads are arranged at equal intervals along length directions of the shear wall members. Reinforcing cage pre-formed holes penetrate through the tops and bottoms of the shear wall members. A plurality of connection male heads are arranged at equal intervals along the length directions of the shear wall members, and the plurality of connection male heads are in one-to-one correspondence with the plurality of connection female heads. One sides of the bottoms of the shear wall members are fixedly connected to folding plates. The present disclosure can achieve the purpose of connecting the shear wall members conveniently and quickly, improving the efficiency and quality of construction.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: April 9, 2024
    Assignee: North China University of Science and Technology
    Inventors: Bo Liu, Juannong Chen, Lin Gao, Yankai Lu
  • Publication number: 20240110479
    Abstract: The present disclosure provides a multi-factor quantitative analysis method for deformation of a neighborhood tunnel. The method includes the following steps: analyzing monitoring data generated at a tunnel site; simulating collapse occurring at a shallow buried section of a tunnel; determining the degree of influence of each factor on the tunnel and a stratum; and determining quantitative influence of each factor on tunnel deformation. The present disclosure can not only provide an accurate theoretical basis for the construction of the shallow buried section of the small-distance tunnel, but also guarantee safety and cost saving during tunnel construction.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Inventors: Yongjun ZHANG, Fei LIU, Sijia LIU, Junyi WANG, Bin GONG, Yingming WU, Ruiquan LU, Qingsong WANG, Qinghui XU, Xiaoming GUAN, Mingdong YAN, Xiangyang NI, Pingan WANG, Shuguang LI, Lin YANG, Ning NAN, Dengfeng YANG
  • Publication number: 20240113750
    Abstract: Aspects of the present disclosure facilitate assessment of radio frequency (RF) exposure from a wireless device supporting multiple-input-multiple-output (MIMO) transmissions using multiple antennas. In certain aspects, MIMO RF exposure distributions for one or more MIMO transmissions are determined and stored in a memory. To assess RF exposure for a MIMO transmission, a processor may retrieve the corresponding MIMO RF exposure distributions from the memory, linearly combine the MIMO RF exposure distributions to obtain a combined MIMO RF exposure distribution, and assess RF exposure compliance based on the combined MIMO RF exposure distribution. In one example, the MIMO RF exposure distribution may include MIMO specific absorption rate (SAR) distributions.
    Type: Application
    Filed: September 23, 2022
    Publication date: April 4, 2024
    Inventors: Jagadish NADAKUDUTI, Lin LU, Paul GUCKIAN
  • Publication number: 20240114469
    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for radio frequency exposure evaluation per surface. A method of wireless communication by a wireless device includes accessing radio frequency (RF) exposure information associated with different surfaces among a plurality of surfaces of the wireless device; and transmitting a signal at a transmit power determined based at least in part on the RF exposure information and an RF exposure limit.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 4, 2024
    Inventors: Jagadish NADAKUDUTI, Lin LU
  • Publication number: 20240113195
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG