Abstract: A processed wafer includes an outer surface, and a treated portion having a depth of 0 to 50 ?m measured from the outer surface. At least a part of the treated portion has an oxygen concentration of less than 13 wt %. A method for processing a wafer includes the steps of: applying a reducing medium on the wafer, the reducing medium is in powder form and including a reducing agent, and at least one of a catalyst and a releasing agent; subjecting the wafer to a reduction reaction at a temperature below Curie temperature of the and under a non-oxidizing atmosphere so as to obtain the aforesaid processed wafer.

Abstract: Techniques and apparatus for operating a wireless communication device pursuant to RF exposure compliance are provided. An example method generally includes: when an RFECS1 of the wireless device is in an online state, controlling, via the RFECS1, at least one of first radio(s) associated with a first RAT or second radio(s) associated with a second RAT, in compliance with an RF exposure limit and based on at least one of first RF exposure information associated with the first radio(s) or second RF exposure information associated with the second radio(s); when the RFECS1 transitions from the online state to being unavailable, obtaining, by an RFECS2 of the wireless device, third RF exposure information associated with the second radio(s); and when the RFECS1 is unavailable, controlling, via the RFECS2, the second radio(s) in compliance with the RF exposure limit and based at least in part on the third RF exposure information.

Abstract: A semiconductor device includes a first stacked structure, a second stacked structure, a first vertical connector, and a second vertical connector. The first stacked structure includes a first stacked wafer and a first bonding layer. The first stacked wafer includes multiple first dielectric bonding interfaces. The second stacked structure includes a second stacked wafer and a second bonding layer. The second stacked wafer includes multiple second dielectric bonding interfaces. The first bonding layer is bonded and electrically connected to the second bonding layer, such that there is a hybrid bonding interface between the first stacked structure and the second stacked structure. The first vertical connector penetrates the first dielectric bonding interfaces and is electrically connected to the first bonding layer. The second vertical connector penetrates the second dielectric bonding interfaces and is electrically connected to the second bonding layer.

Abstract: A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.

Abstract: A wafer structure and a manufacturing method thereof are provided. The wafer structure includes a substrate structure, a first dielectric layer, multiple test pads, a second dielectric layer, and multiple bond pads. The first dielectric layer is disposed on the substrate structure. The test pads are disposed in and exposed outside the first dielectric layer. Each test pad has a probe mark. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a top surface away from the test pads. Multiple bond pads are disposed in and exposed outside the second dielectric layer. Each bond pad is electrically connected to the corresponding test pad. The bond pads have bonding surfaces away from the test pads. The bonding surfaces are flush with the top surface. In the normal direction of the substrate structure, each bond pad does not overlap the probe mark of the corresponding test pad.

Abstract: Simultaneous primary and secondary radio frequency link transmissions are described. The transmissions are restricted to within radio frequency exposure limits. A method is described that includes determining an unused power margin between an average transmit power of a primary radio and the transmit power limit. A combination of a portion of the unused power margin and a secondary reserve transmit power are allocated to the secondary radio. The average transmit power of the secondary radio is restricted to within the combination.

Abstract: A virtual image display device and a stereoscopic image establishing method are provided. The virtual image display device includes a head-mounted display and an accessory. The head-mounted display performs an image capturing operation on a first region of an object to obtain first image information. The accessory has a first image capturing device for performing an image capturing operation on a second region of the object to obtain second image information. The head-mounted display establishes stereoscopic image information of the object based on the first image information and the second image information.

Abstract: This application provides a wireless headset, and relates to the field of TWS wireless headsets. The wireless headset includes a headset housing and a headset assembly accommodated in the headset housing. The headset assembly includes a microphone. The headset housing includes a bottom housing, the bottom housing includes a first bottom housing part and a second bottom housing part that are separated by using an insulating material, the first bottom housing part is a positive charging electrode, and the second bottom housing part is a negative charging electrode.

Abstract: A semiconductor device includes a semiconductor stack, including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad, adjacent to a first edge of the semiconductor device; a second electrode pad, adjacent to a second edge of the semiconductor device; and an insulating layer covering the semiconductor stack, including one or more first openings adjacent to the first edge and one or more second openings adjacent to the second edge, and wherein the one or more first openings and the one or more second openings expose the first semiconductor layer; wherein the one or more first openings includes a first maximum length, and the one or more second openings includes a second maximum length greater than the first maximum length.

Abstract: An image capturing device and an image capturing method thereof are provided. The image capturing device includes a plurality of infrared light sources, an image capturer and a controller. The infrared light sources respectively have a plurality of light types. The image capturer is configured to capture image information. The controller is coupled to the infrared light sources and the image capturer. The controller turns on or turns off each of the infrared light sources according to light intensity information, wherein at least one of the infrared light sources is turned on during an image capturing operation.

Abstract: A 3D stack package structure includes a first chip, a second chip, a through-silicon via (TSV), and a multi-layer protective structure. The second chip is bonded to the first chip. The second chip includes an interconnect structure composed of multiple metal layers and a plurality of vias respectively connecting upper and lower layers of the multiple metal layers. The TSV extends through the second chip. The multi-layer protective structure is disposed within the second chip and surrounds the TSV. The multi-layer protective structure includes: multiple protective layers, each having an opening for passage of the TSV; and a plurality of sealing rings, respectively connecting upper and lower layers of the multiple protective layers and surrounding the TSV.

Abstract: A semiconductor package structure includes a control unit and a memory unit. The control unit includes a first wafer and a second wafer that are vertically stacked. The memory unit is disposed on the second wafer of the control unit. The memory unit includes multiple third wafers and a fourth wafer that are stacked vertically. The memory unit overlaps the control unit in a normal direction of the semiconductor package structure. In addition, a manufacturing method of the semiconductor package structure is provided.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may identify an available energy for uplink transmission of a plurality of communication links of the UE. The UE may configure, from the available energy, a first set of energy allocations for the plurality of communication links. The UE may configure a second set of energy allocations for one or more communication links of the plurality of communication links, wherein the second set of energy allocations are allocated from a remainder of the available energy after the first set of energy allocations are allocated. The UE may transmit based at least in part on at least one of the first set of energy allocations or the second set of energy allocations. Numerous other aspects are described.

Abstract: A package structure includes a conductive feature structure, a die, an adhesive layer, an insulator, a through via, and an encapsulant. The die is disposed over the conductive feature structure. The adhesive layer is disposed below the die. The insulator is disposed between the adhesive layer and a polymer layer of the conductive feature structure. The through via extends through the insulator to connect to the conductive feature structure. The encapsulant is disposed on the insulator and the conductive feature structure, laterally encapsulating the die and the through via, and between the through via and the insulator. The insulator has a coefficient of thermal expansion less than a coefficient of thermal expansion of the encapsulant.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may allocate a first amount of power to one or more radios for a time window based on radio frequency (RF) exposure information and one or more other criteria. The UE may allocate a second amount of power to a selected channel or communication utilized by at least one radio of the one or more radios for one or more time frames within the time window based on the first amount of power allocated to the at least one radio for the time window. The UE may transmit the selected channel or communication based on the first amount of power or the second amount of power. Numerous other aspects are described.

Abstract: Provided are a mutant of an immunoglobulin degrading enzyme IdeE, a protein comprising the mutant, and a use of a composition and a kit in preparation of a drug for reducing the level of IgG in a subject. The mutant has amino acid substitution, N-terminal truncated and/or C-terminal truncated on one or more of positions 8, 10, 24, 59, 97, and 280 of the amino acid sequence shown in SEQ ID NO: 2, and the mutant has the function of the immunoglobulin degrading enzyme IdeE, and has higher activity and thermal stability than wild-type IdeE.

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: A hardware acceleration circuit, a chip, a data processing acceleration method, an accelerator, and a device are provided. The circuit includes: a lookup table circuit, configured to: in response to an ith element in an input data set, output an exponential function value corresponding to a first index value of the ith element based on a first lookup table, and/or output a reciprocal of the exponential function value corresponding to a second index value of the ith element based on a second lookup table; an adder, configured to output an addition operation result of exponential function values corresponding to at least some elements in the input data set; and a multiplier, configured to output a multiplication operation result of a reciprocal of an exponential function value corresponding to the ith element and the addition operation result, to obtain a reciprocal of a specific function value corresponding to the ith element.

Abstract: A hardware acceleration circuit, a data processing acceleration method, a chip, and an accelerator are provided. The hardware acceleration circuit includes: an exponential function module, configured to obtain exponential function values of a plurality of data elements in a data set; an adder, configured to obtain an addition operation result of the exponential function values; a first processing circuit, configured to perform preset processing on the addition operation result, to process the addition operation result into at least first data and second data; a second processing circuit, configured to perform preset processing on at least the first data and the second data, to obtain a reciprocal of the addition operation result; and a third processing circuit, configured to perform preset processing on an exponential function value of an ith data element in the data elements and the reciprocal, to obtain a specific function value of the ith data element.

Abstract: A hardware acceleration circuit, a data processing acceleration method, a chip, and an accelerator are provided. The circuit includes: a storage module, configured to store first and second lookup tables; a lookup table circuit, configured to output, in response to respective index values of data elements and based on the first lookup table, exponential function values corresponding to the data elements; and output, in response to an index value of an addition operation result and based on the second lookup table, a reciprocal corresponding to the addition operation result; an adder, configured to obtain the addition operation result by adding the exponential function values for the lookup table circuit; and a multiplier, configured to output a multiplication operation result of an exponential function value of an ith data element and the reciprocal of the addition operation result, to obtain a Softmax function value of the ith data element.