Patents by Inventor Lin Lu

Lin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10391871
    Abstract: This disclosure provides systems, methods and apparatus for mitigating electromagnetic radiation emissions. In one aspect, a power transfer device of a wireless electric vehicle charging (WEVC) system is provided. The power transfer device includes a ferrite material and at least one electrically conductive coil. The ferrite material and the at least one coil are configured to wirelessly transfer energy either from or to a second power transfer device of the WEVC system. The power transfer device further includes at least one shield comprising a plurality of electrically conducting regions and one or more electrically insulating regions. The plurality of electrically conducting regions and one or more electrically insulating regions are configured to mitigate electromagnetic radiation emissions from the WEVC system that do not contribute to the wireless power transfer between the at least one electrically conductive coil and the second power transfer device.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: August 27, 2019
    Assignee: WiTricity Corporation
    Inventors: Lin Lu, Paul Guckian, Jagadish Nadakuduti
  • Publication number: 20190252259
    Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.
    Type: Application
    Filed: February 11, 2018
    Publication date: August 15, 2019
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Chun-Hsien Lin, Wei-Hao Huang, Kai-Teng Cheng
  • Patent number: 10381309
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Kai-Chiang Wu, Albert Wan
  • Publication number: 20190244834
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The first redistribution structure has a dielectric layer and a feed line disposed on the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The insulation encapsulation has a protrusion laterally wraps around the feed line. The insulation encapsulation has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The second redistribution structure is disposed on the die and the insulation encapsulation.
    Type: Application
    Filed: April 21, 2019
    Publication date: August 8, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Patent number: 10357151
    Abstract: Systems and methods for using an interocular inhibition procedure (IIP) for discriminating between anisometropic amblyopia and myopia, two disorders commonly confused in visual examination without proper optical correction. Opaque and translucent patching are positioned over the fellow (or untested) eye resulting in different contrast sensitivities in the amblyopic (or tested) eye. A pinhole aperture may be used for identifying amblyopia and myopia/hyperopia.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: July 23, 2019
    Assignees: OHIO STATE INNOVATION FOUNDATION, ADAPTIVE SENSORY TECHNOLOGY, BEIJING JUEHUA MEDICAL TECHNOLOGY CO., LTD., INSTITUTE OF PSYCHOLOGY, CHINESE ACADEMY OF SCIENCES
    Inventors: Zhong-Lin Lu, Chang-Bing Huang, Wuli Jia, Luis A. Lesmes, Jiawei Zhou
  • Patent number: 10361342
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad electrically connected to the first semiconductor layer; a second pad comprising multiple sidewalls electrically connected to the second semiconductor layer; and a metal layer formed on the semiconductor stack, wherein the metal layer surrounds the multiple sidewalls of the second pad and the metal layer is separated from the second pad.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 23, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Wen-Hung Chuang, Tzu-Yao Tseng, Cheng-Lin Lu, Chi-Shiang Hsu, Tsung-Hsun Chiang, Bo-Jiun Hu
  • Patent number: 10353137
    Abstract: A quantum dot (QD) light source component, a backlight module and a liquid crystal display device are disclosed. The QD light source component includes a bracket, a light source, and a QD unit, the bracket is formed with a groove; the light source is arranged at bottom center of the groove of the bracket for emitting light; the QD unit is arranged at opening of the groove of the bracket, and includes an upper substrate, a lower substrate and a QD layer; at least one of the upper substrate and lower substrate is provided with a substrate groove, the upper substrate and lower substrate form enclosure space through the substrate groove; the QD layer is located within the substrate groove, and emits light under excitation of light emitted from light source, where the QD layer is thicker at its central position than at its edge position.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 16, 2019
    Assignees: HISENSE ELECTRIC CO., LTD., HISENSE USA CORPORATION, HISENSE INTERNATIONAL CO., LTD.
    Inventors: Fulin Li, Lin Lu
  • Publication number: 20190206057
    Abstract: Systems and methods are described herein for modeling neural architecture. Regions of interest of a brain of a subject can be identified based on image data characterizing the brain of the subject. the identified regions of interest can be mapped to a connectivity matrix. The connectivity matrix can be a weighted and undirected network. A multivariate transformation can be applied to the connectivity matrix to transform the connectivity matrix into a partial correlation matrix. The multivariate transformation can maintain a positive definite constraint for the connectivity matrix. The partial correlation matrix can be transformed into a neural model indicative of the connectivity matrix.
    Type: Application
    Filed: September 13, 2017
    Publication date: July 4, 2019
    Applicants: Ohio State Innovation Foundation, The Penn State Research Foundation, University of North Carolina, University of San Francisco
    Inventors: Skyler Cranmer, Bruce Desmarais, Shankar Bhamidi, James Wilson, Matthew Denny, Zhong-Lin Lu, Paul Stillman
  • Patent number: 10340423
    Abstract: A light-emitting device includes a semiconductor structure comprising a surface and a side wall inclined to the surface, wherein the semiconductor structure comprises a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, and the second semiconductor layer comprises a first edge and a first area; and a reflective layer located on the semiconductor structure and comprising an outer edge and a second area; wherein a distance between the first edge and the outer edge is between 0 ?m and 10 ?m, and the second area of the reflective layer is not less than 80% of the first area of the second semiconductor layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 2, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Wen-Hung Chuang, Tzu-Yao Tseng, Cheng-Lin Lu
  • Publication number: 20190192039
    Abstract: Method and systems provide a tool to quantify sensory maps of the brain. Cortical surfaces are conformally mapped to a topological disk where local geometry structures are well preserved. Retinotopy data are smoothed on the disk domain to generate a curve that best fits the retinotopy data and eliminates noisy outliers. A Beltrami coefficient map is obtained, which provides an intrinsic conformality measure that is sensitive to local changes on the surface of interest. The Beltrami coefficient map represents a function where the input domain is locations in the visual field and the output is a complex distortion measure at these locations. This function is also invertible. Given the boundaries and the Beltrami map of a flattened cortical region, a corresponding visual field can be reconstructed. The Beltrami coefficient map allows visualization and comparison of retinotopic map properties across subjects in the common visual field space.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Yalin Wang, Duyan Ta, Zhong-Lin Lu
  • Publication number: 20190194686
    Abstract: A host cell for protein expression having a lower expression level of a gene, as compared to a wild-type cell, wherein the gene is selected from HDAC8, Dab2, Caspase3, Sys1, Ergic3, Grasp, Trim 23, or a combination thereof. The host cells are CHO cells. The lower expression level of the gene results from RNA interference, which may be achieved by transfecting a vector that contains an shRNA targeting the gene.
    Type: Application
    Filed: September 29, 2018
    Publication date: June 27, 2019
    Applicant: Development Center for Biotechnology
    Inventors: HSIN-LIN LU, CHIEN-I LIN, CHAO-YI TENG
  • Patent number: 10332978
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang
  • Patent number: 10300160
    Abstract: A plasma liquid generating device includes a tube, a plasma generating module, a flow limiting unit, and a position limiting member. The tube has at least an air inlet and a flow channel outlet. The plasma generating module is disposed adjacent to the air inlet and configured to generate plasma. The flow limiting unit is detachably disposed in the tube, and a distance between the flow limiting unit and the flow channel outlet is greater than a distance between the air inlet and the flow channel outlet. The position limiting member is detachably disposed at the flow channel outlet to limit the position of the flow limiting unit.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: May 28, 2019
    Assignee: AMSALP BIOMEDICAL CO., LTD
    Inventors: Jen-Chieh Lu, Yin-Lin Lu
  • Publication number: 20190157206
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Kai-Chiang Wu, Albert Wan
  • Publication number: 20190148600
    Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a surrounding part surrounding the semiconductor structure and exposing a surface of the first semiconductor layer; a first insulating structure formed on the semiconductor structure, including a plurality of protrusions covering the surface of the first semiconductor layer and a plurality of recesses exposing the surface of the first semiconductor layer; a first contact portion formed on the surrounding part and contacting the surface of the first semiconductor layer by the plurality of recesses; a first pad formed on the semiconductor structure; and a second pad formed on the semiconductor structure.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Wen-Hung CHUANG, Cheng-Lin LU
  • Publication number: 20190139890
    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
  • Patent number: 10276404
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chung-Hao Tsai, Chun-Lin Lu, Yen-Ping Wang, Che-Wei Hsu
  • Publication number: 20190123017
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hung-Jen Lin
  • Patent number: 10268405
    Abstract: A memory interface includes a buffer for storing requests for accessing a volatile memory, which includes at least two ranks of memory cell of a memory channel The memory interface monitors the requests to access each rank in the buffer. Upon detecting from the requests that a given rank of the at least two ranks is to be idle for a time period exceeding a time threshold, the circuitry signals a controller to command the given rank to enter a self-refresh mode independent of a refresh mode of other ranks. The memory interface is coupled to a processor, which executes an operating system (OS) kernel to prioritize memory allocation from a prioritized rank of the at least two ranks over the given rank, and migrates allocated memory blocks from the given rank to the prioritized rank to increase a probability of idleness of the given rank.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 23, 2019
    Assignee: MediaTek, Inc.
    Inventors: Chia-Lin Lu, Min-Hua Chen
  • Patent number: 10269588
    Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang