Patents by Inventor Lin Lu

Lin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200177223
    Abstract: An apparatus including a housing; sensors configured to sense one or more locations upon which a user is gripping the housing; sensors including antenna modules configured to transmit a signal based on the one or more locations upon which the user is gripping the housing. Another aspect relates to an apparatus including a housing; a set of antenna modules situated proximate at different surface locations along the housing; and a controller configured to operate the set of antenna modules to determine at least one or more electromagnetic leakage coupling between at least one pair of antenna modules of the set. In this aspect, the controller may be configured to select one or more of the set of antenna modules for transmitting a signal based on the one or more electromagnetic leakage coupling associated with one or more of the different locations where a user grips the housing, respectively.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Inventors: Udara FERNANDO, Lin LU
  • Publication number: 20200165632
    Abstract: Provided are compositions and methods of transducing/transfecting cells with a molecule, such as a nucleic acid (e.g., plasmid), at high efficiency. High efficiency transduced/transfected cells can, when transduced with a nucleic acid that encodes a protein or comprises a sequence that is transcribed into a transcript of interest, produce high amounts of protein and/or transcript. High efficiency transduced/transfected cells can, when transduced with plasmids comprising (i) nucleic acids encoding AAV packaging proteins and/or nucleic acids encoding helper proteins; and (ii) a transgene that encodes a protein or is transcribed into a transcript of interest; produce high amounts of recombinant rAAV vector.
    Type: Application
    Filed: June 6, 2018
    Publication date: May 28, 2020
    Applicant: Spark Therapeutics, Inc.
    Inventors: Guang QU, Lin LU, Jesusa JOSUE-ALMQVIST, John Fraser WRIGHT
  • Publication number: 20200165391
    Abstract: A polyimide polymer includes a first monomeric unit from dianhydride and a second monomeric unit from diamine, and the dianhydride includes 1,4-bis(3,4-dicarboxyphenoxy)benzene dianhydride (HQDPA), and coefficient of thermal expansion (CTE) is below 60 ppm/° C. The polyimide film includes a film layer, and the film layer includes the above polyimide polymer. The film layer optionally includes a pigment and an inorganic nanoparticle. Therefore, the thermal resistance and the transparency of the polyimide film are improved, and the polyimide film having high thermal resistances with different colors is available.
    Type: Application
    Filed: December 12, 2018
    Publication date: May 28, 2020
    Applicant: MORTECH CORPORATION
    Inventors: Der-Jen SUN, Chi Sheng CHEN, Chang Lin LU
  • Patent number: 10665537
    Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ling Hwang, Chun-Lin Lu, Kai-Chiang Wu
  • Publication number: 20200157509
    Abstract: Described herein are specific CHO genomic sites for targeted insertion of exogenous genes. The sites are located within a sequence selected from SEQ ID NOs: 1-16.
    Type: Application
    Filed: December 19, 2017
    Publication date: May 21, 2020
    Inventors: Hsuan-Pu CHEN, Hsin-Lin LU, Chien-I LIN, Hsueh-Lin LU, Tao-Tien CHEN
  • Publication number: 20200152570
    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.
    Type: Application
    Filed: December 8, 2019
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Nan-Chin Chuang
  • Patent number: 10651344
    Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a surrounding part surrounding the semiconductor structure and exposing a surface of the first semiconductor layer; a first insulating structure formed on the semiconductor structure, including a plurality of protrusions covering the surface of the first semiconductor layer and a plurality of recesses exposing the surface of the first semiconductor layer; a first contact portion formed on the surrounding part and contacting the surface of the first semiconductor layer by the plurality of recesses; a first pad formed on the semiconductor structure; and a second pad formed on the semiconductor structure.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: May 12, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Wen-Hung Chuang, Cheng-Lin Lu
  • Patent number: 10652833
    Abstract: In certain aspects, a method implemented in a wireless device includes determining a specific absorption rate (SAR) distribution for a first wireless communication technology, determining a power density (PD) distribution for a second wireless communication technology, and combining the SAR distribution and the PD distribution to generate a combined RF exposure distribution. The method also includes determining at least one first maximum allowable power level and at least one second maximum allowable power level for a future time slot based on the combined RF exposure distribution, setting at least one transmission power limit for a first transmitter in the future time slot based on the at least one first maximum allowable power level, and setting at least one transmission power limit for a second transmitter in the future time slot based on the at least one second maximum allowable power level.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 12, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jagadish Nadakuduti, Lin Lu, Paul Guckian, Mingming Cai, Junsheng Han, Udara Fernando, Raghu Challa
  • Patent number: 10646155
    Abstract: The invention provides a method of generating an adaptive partial report for an observer with an apparatus comprising a display, a user interface, and a processor. The apparatus can be a computer system or an electronic device, for example. The method includes the processor characterizing an iconic memory decay function for the observer. The characterization includes determining a prior for a plurality of parameters. The method further includes the processor determining a first stimulus for a first trial based on the prior for the plurality of parameters, the display generating the stimulus for viewing by the observer, the user interface receiving input for the first trial and in response to the stimulus, the processor revising respective parameter values for the parameters based on the received input, and the processor determining a new stimulus for a next trial based on the revised parameter values.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 12, 2020
    Assignees: OHIO STATE INNOVATIVE FOUNDATION, ADAPTIVE SENSORY TECHNOLOGY
    Inventors: Zhong-Lin Lu, Jongsoo Baek, Luis A. Lesmes
  • Publication number: 20200144193
    Abstract: A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.
    Type: Application
    Filed: January 7, 2020
    Publication date: May 7, 2020
    Inventors: CHEN-HUA YU, KAI-CHIANG WU, CHUN-LIN LU
  • Publication number: 20200118952
    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.
    Type: Application
    Filed: December 15, 2019
    Publication date: April 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Nan-Chin Chuang
  • Publication number: 20200114429
    Abstract: Provided is a method of making colloidal platinum nanoparticles. The method includes three consecutive steps: dissolving platinum powders by a halogen-containing oxidizing agent in HCl to obtain an inorganic platinum solution containing an inorganic platinum compound; adding a reducing agent into the same reaction vessel to form a mixture solution and heating the mixture solution to undergo a reduction reaction and produce a composition containing platinum nanoparticles, residues and a gas, and guiding the gas out of the reaction vessel, wherein the amount of the residues is less than 15% by volume of the mixture solution; and adding a medium into the same reaction vessel to disperse the platinum nanoparticles to obtain colloidal platinum nanoparticles. The method is simple, safe, time-effective, cost-effective, and has the advantage of high yield.
    Type: Application
    Filed: April 23, 2019
    Publication date: April 16, 2020
    Inventors: Lin LU, Kuei-Sheng FAN, Chun-Lun CHIU CHIU, Han-Wu YEN, Hao-Chan HSU, Chia-Yi LIN, Chi-Jiun PENG, Cheng-Ding WANG, Jim-Min FANG
  • Publication number: 20200118971
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Tzu-Chun Tang, Chuei-Tang Wang, Chun-Lin Lu, Wei-Ting Chen, Vincent Chen, Shou-Zen Chang, Kai-Chiang Wu
  • Publication number: 20200111753
    Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 9, 2020
    Inventors: CHUEI-TANG WANG, VINCENT CHEN, TZU-CHUN TANG, CHEN-HUA YU, CHING-FENG YANG, MING-KAI LIU, YEN-PING WANG, KAI-CHIANG WU, SHOU ZEN CHANG, WEI-TING LIN, CHUN-LIN LU
  • Publication number: 20200105675
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Application
    Filed: March 5, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Patent number: 10595282
    Abstract: Certain aspects of the present disclosure propose methods for determining power level of one or more transmitters based on a power level of a primary transmitter when the transmitters are located in close proximity of each other. The power levels may be determined such that a combined power of all the transmitters is compliant with regulatory radio frequency (RF) safety requirements. For certain aspects, power level of the lower priority transmitters may be determined utilizing one or more look-up tables. For another aspect, power level of the lower priority transmitters may be calculated using an algorithm based on the power level of the priority transmitter. In aspects, the power level of lower priority transmitters and the time duration for which the transmitters are active may be selected dynamically so that the time averaged power of the transmitters for a defined period of time falls below the RF exposure limit.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: John Forrester, Paul A. Guckian, Lin Lu, Reza Shahidi, Amit Mahajan, Walid M. Hamdy, Francis M. Ngai
  • Publication number: 20200049644
    Abstract: A temperature and humidity sensor module sensing method for enabling a temperature and humidity sensor in an electric product to provide the detected humidity message to a micro control unit for determination. According to the characteristic curve of a known humidity sensor, the micro control unit determines that the humidity value rising slope exceeds a predetermined rising slope for a specific period of time, or the relative humidity rises a predetermined percentage for a specified period of time, or a high humidity limit continues for a specific period of time, indicating that the surface of the temperature and humidity sensor is attached or condensed with water molecules. Then, the micro control unit controls the heating element to heat-dry the temperature and humidity sensor, keeping the temperature and humidity sensor in the optimal working condition.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 13, 2020
    Inventors: Shang-Jung WU, Chun-Lin LU, Chia-Hung WANG, Chin-Feng CHEN
  • Publication number: 20200049643
    Abstract: A temperature and humidity sensor module heat drying structure used in an electrical product is disclosed to include a temperature and humidity sensor, a heating element and a micro control unit. When the humidity value detected by the temperature and humidity sensor surpasses a predetermined reference value, the micro control unit controls the heating element to heat the temperature and humidity sensor, evaporating water from the surface of the temperature and humidity sensor. After a period of time, when the humidity value detected by the temperature and humidity sensor is lower than the predetermined reference value, the heating operation is stopped, keeping the temperature and humidity sensor in optimal working condition.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 13, 2020
    Inventors: Shang-Jung WU, Chun-Lin LU, Chia-Hung WANG, Chin-Feng CHEN
  • Publication number: 20200044116
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Application
    Filed: August 1, 2019
    Publication date: February 6, 2020
    Inventors: Chao-Hsing CHEN, Cheng-Lin LU, Chih-Hao CHEN, Chi-Shiang HSU, I-Lun MA, Meng-Hsiang HONG, Hsin-Ying WANG, Kuo-Ching HUNG, Yi-Hung LIN