Abstract: In a multi-cloud computing environment comprising a plurality of cloud platforms, wherein one cloud platform is a source of a model and a data set and further wherein the model is to be executed against the data set on one or more of the other cloud platforms, the method maintains a decentralized architecture comprising a file system and a message bus, wherein the file system comprises a plurality of decentralized file system nodes corresponding to the plurality of cloud platforms, and the message bus comprises a plurality of decentralized message bus nodes corresponding to the plurality of cloud platforms. Further, the method manages sharing of the model and the data set via at least a portion of the decentralized file system nodes and manages messaging related to execution of the model against the data set via at least a portion of the decentralized message bus nodes.

Abstract: Disclosed herein is a combination of genomic sequences whose methylation patterns have utility for the improved detection and differentiation between colorectal neoplasms. Further disclosed herein are methods, nucleic acids and kits for detecting or differentiating between colorectal neoplasms.

Abstract: An IC device includes a first power terminal, an IO pad, a first ESD protection device coupled between the first power terminal and IO pad, a first trigger current source device coupled between the first power terminal and IO pad, and a semiconductor substrate over which the first ESD protection device and first trigger current source device are formed. The first ESD protection device includes a parasitic BJT having a collector and an emitter coupled between the IO pad and first power terminal, and a base coupled via a substrate resistance to a well tap coupled to the first power terminal. The first trigger current source device, in response to an ESD voltage on the IO pad, becomes conductive and causes discharge of the ESD voltage through the first ESD protection device to the first power terminal.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: Embodiments of the present disclosure provide a method, apparatus and computer program product for resource scheduling. The method comprises obtaining a processing requirement for a deep learning task, the processing requirement being specified by a user and at least including a requirement related to a completion time of the deep learning task. The method further comprises determining, based on the processing requirement, a resource required by the deep learning task such that processing of the deep learning task based on the resource satisfies the processing requirement. Through the embodiments of the present disclosure, the resources can be scheduled reasonably and flexibly to satisfy the user's processing requirement for a particular deep learning task without requiring the user to manually specify the requirement on the resources.

Abstract: An integrated circuit includes a diode string, a first transistor, a second transistor, and a third transistor. The diode string is coupled between a first reference voltage pin and an input/output (I/O) pad. A first terminal of the second transistor is coupled to a first node, and a gate terminal of the second transistor is coupled to a second reference voltage pin. In response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to a gate terminal of the first transistor.

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Abstract: A device is disclosed herein. The device includes an electrostatic discharge (ESD) detector, a bias generator, and an ESD driver including at least two transistors coupled to each other in series. The ESD detector is configured to detect an input signal and generate a detection signal in response to an ESD event being detected. The bias generator is configured to generate a bias signal according to the detection signal. The at least two transistors are controlled according to the bias signal and a logic control signal, and the input signal is applied across the at least two transistors.

Abstract: Provided is a gathering mechanism for adapter, including a cylindrical body having a plurality of accommodating units indentedly and spacedly mounted on a surface of the cylindrical body in an axial direction thereof; a plurality of adapters, each of which is provided with a flexible latching member on one end thereof, and the other end of the flexible latching member is a free end provided with a bulged joggle unit for being received in a corresponding accommodating unit; and an outer sleeve sleeving the cylindrical body and having at least one cut groove mounted in an axial direction of the outer sleeve for allowing the flexible latching member to transversely enter and exit the therethrough, and wherein a width of the cut groove is smaller than a width of the bulged joggle unit, thereby forming a limiting engagement. Thus, multiple adapters can be tidily gathered and protected.

Abstract: Provided is a gathering mechanism for adapter, including a cylindrical body having a plurality of accommodating units indentedly and spacedly mounted on a surface of the cylindrical body in an axial direction thereof; a plurality of adapters, each of which is provided with a flexible latching member on one end thereof, and the other end of the flexible latching member is a free end provided with a bulged joggle unit for being received in a corresponding accommodating unit; and an outer sleeve sleeving the cylindrical body and having at least one cut groove mounted in an axial direction of the outer sleeve for allowing the flexible latching member to transversely enter and exit the therethrough, and wherein a width of the cut groove is smaller than a width of the bulged joggle unit, thereby forming a limiting engagement. Thus, multiple adapters can be tidily gathered and protected.

Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

Abstract: Embodiments of the present disclosure relate to an apparatus and method for facilitating access to data in a distributed storage system by using a processing unit configured to collect information related to running status of the distributed storage system; obtain metadata related to data stored in the distributed storage system; in response to a request from a client, provide to the client the information related to running status and metadata related to data to be accessed; and extend storage nodes in the distributed storage system so that the client can directly access the storage nodes by using the information related to running status and the metadata related to data to be accessed. Other embodiments are also disclosed.

Abstract: The present disclosure provides a connector assembly comprising a cage and a heat sink. The cage has a receiving space and a wall constituting the receiving space, the wall is formed with a window which is communicated with the receiving space and two latching plates which are provided to two sides of the window and extend away from the receiving space, each latching plate is integrally formed with a latching protrusion, the latching protrusion has a guiding portion and a latching portion, a protruding amount of the guiding portion from the latching plate gradually increases as a distance of the guiding portion from the receiving space decreases, the latching portion is positioned to a tip end surface of the guiding portion.

Abstract: An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

Abstract: The present disclosure provides a power management apparatus, method and system. The apparatus comprises: a client management module for configuring power management client module(s) on one or more clients, the power management client module being for power management of the client; a data collector module for collecting, via the power management client module(s), data related to the power management of one or more user accounts on one or more clients; and a repository module for storing the collected data.

Abstract: Provided are a photoalignment method and a photoalignment device, including: adjusting direction of light ray emitted from light source so that first angle is formed between that and XOY plane, and second angle is formed between projection of that on XOY plane and Y-axis; adjusting angle of polarizing plate so that it is parallel to XOY plane, and its light transmission axis is parallel to projection of that on XOY plane; moving array substrate along negative direction of Y-axis to perform exposure operation on array substrate; and moving color filter substrate, which rotated by 180 degrees, in negative direction of Y-axis to perform exposure operation on color filter substrate, wherein color filter substrate has exposure regions which are completely identical, in position and number, to those of array substrate, and each exposure region is exposed to light in identical direction to that of corresponding exposure region of array substrate.

Abstract: Implementations of the present disclosure relate to a method, apparatus and computer program product for processing a computing task. The method comprises: obtaining status information of multiple computing resources; in response to receiving a neural network model-based computing task, determining configuration information of multiple layers associated with the neural network model; obtaining parameter data associated with at least one part of the multiple layers on the basis of the configuration information; and based on the status information and the parameter data, selecting from the multiple computing resources a group of computing resources for processing the computing task. According to the example implementations of the present disclosure, multiple computing resources may be utilized sufficiently, and it may be guaranteed that a load balance may be stricken between the multiple computing resources.