Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.

Abstract: A semiconductor structure includes a first dielectric layer, a second dielectric layer on the first dielectric layer, a capacitor structure in the first dielectric layer and the second dielectric layer, a third dielectric layer on the second dielectric layer, a word line, a channel structure, and a gate dielectric. The word line is located in the third dielectric layer and extends across the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the word line and a portion of the third dielectric layer. The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is between a sidewall of the word line and the channel structure, and the second portion is between an inner sidewall of the third dielectric layer and the channel structure.

Abstract: A dynamic random access memory includes an array region, a bottom capacitor array located in the array region, and a top capacitor array located in the array region and located on the bottom capacitor array. The bottom capacitor array is single-sided capacitor array. The top capacitor is a double-sided capacitor array.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: The present disclosure provides a method and electronic apparatus for modifying pages of an electronic document, and the method is performed by the electronic apparatus and comprises the following steps: opening a first user operation interface; detecting whether a first input region is selected; when it is detected that the first input region is selected, displaying a plurality of first pages of a first electronic document on a page preview region and determining a first page change position located in the plurality of first pages according to a first operation event; detecting whether a second input region is selected; when it is detected that the second input region is selected, displaying a plurality of second pages of a second electronic document on the page preview region and determining at least one second page of the plurality of second pages according to a second operation event; and adding the at least one second page to the first page change position according to a third operation event.

Abstract: This disclosure provides a method and a user apparatus for generating and applying a translation marker, and the method is performed by the user apparatus and comprises: opening an electronic document on a user operation interface; selecting at least one text string in the electronic document according to a first triggering event; and when a translation option is detected to be selected, performing the following steps: generating a code corresponding to the selected text string by using an operation function; and displaying a first translated text string of the first translation record on the user operation interface and generating a first translation marker associated with the first translated text string on the electronic document when it is determined that a first translation record associated with the code exists in the user apparatus.

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Abstract: A phosphinated (2,6-dimethylphenyl ether) oligomer, preparation method thereof and cured product. The phosphinated (2,6-dimethylphenyl ether) oligomer includes a structure represented by Formula (1): wherein X is a single bond, —CH2—, —O—, —C(CH3)2— or R?0, R0, R1, R2 and R3 are independently hydrogen, C1-C6 alkyl or phenyl; n and m are independently an integer from 0 to 300; p and q are independently an integer from 1 to 4; Y is hydrogen, U and V are independently an aliphatic structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.

Abstract: A memory includes a data storage device, a data processing device, and a contact element. The data processing device is disposed over the data storage device. The contact element is disposed between the data storage device and the data processing device. The contact element electrically connects the data storage device with the data processing device.

Abstract: A method of manufacturing a semiconductor memory is provided. The method includes steps of forming a data storage device; forming a data processing device over the data storage device; forming a contact element electrically connected to the data storage device; and forming a data processing device over the data storage device and electrically connected to the contact element.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A semiconductor device includes a device layer with a semiconductor element, a first dielectric layer on the device layer, a first conductive line on the device layer and surrounded by the first dielectric layer, and a second dielectric layer on the first dielectric layer and around the first conductive line. The semiconductor includes a spacer disposed on the first conductive line and abutting a sidewall of the second dielectric layer, and a first conductive via disposed on the first conductive line and the spacer. The first conductive via includes a first segment positioned over the spacer and including a first width, and a second segment positioned between the first segment the first conductive line and including a second width. The first width is larger than the second width.