Patents by Inventor Lin Shih

Lin Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11699635
    Abstract: A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: July 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Pei-Jhen Wu
  • Publication number: 20230207473
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer, an etch stop layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The etch stop layer includes silicon nitride and is disposed between the semiconductor substrate and the electrical insulating and thermal conductive layer. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Application
    Filed: February 12, 2023
    Publication date: June 29, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Publication number: 20230202342
    Abstract: A control method of a hybrid electric power supply system used by a hybrid electric vehicle comprises obtaining a gradient of the hybrid electric vehicle, a throttle depth, and a power of an electric device, and calculating a required electric power; obtaining a State Of Charge value of two sets of power sources, and obtaining a power distribution value according to the SOC values and power demand; obtaining real-time output power change values of the two sets of power sources, and using double-level fuzzy energy control to obtain a smooth energy distribution value according to output power changes of the two sets of power sources; and obtaining respective output powers of the two sets of power sources according to the smooth energy distribution value, and controlling a Direct Current converter of the hybrid electric vehicle according to final two sets of output power values.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Inventors: PO-LIN SHIH, CHI-SHENG WU, CHIH-HSIEN CHUNG, SHIH-CHANG TSENG, GWO-HUEI YOU, KUO-KUANG JEN
  • Patent number: 11665888
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: May 30, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
  • Patent number: 11658070
    Abstract: A method of forming a semiconductor structure includes following steps. A first wafer is bonded to a second wafer, in which the first wafer includes a first substrate and a first conductive pad above a first surface of the first substrate, and the second wafer comprises a second substrate and a second conductive pad above a second surface of the second substrate. A mask layer is formed above the first substrate. The mask layer and the first substrate are etched to form a first opening in the first substrate. A sacrificial spacer is formed in the first substrate at a sidewall of the first opening. The first conductive pad is etched to form a second opening communicated to the first opening. A conductive material is filled in the first opening and the second opening to form a conductive structure interconnecting the first and second conductive pads.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: May 23, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Patent number: 11647623
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: May 9, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Tseng-Fu Lu, Jeng-Ping Lin
  • Publication number: 20230061843
    Abstract: An electronic package is provided. The electronic package includes a first circuit structure, a second circuit structure, and an underfill. The second circuit structure is disposed over the first circuit structure. The underfill is disposed between the first circuit structure and the second circuit structure. An inner portion of the underfill has an inner lateral surface adjacent to and is substantially conformal with a lateral surface of the second circuit structure. A first top end of the inner lateral surface is not level with a top surface of the second circuit structure. An outer portion of the underfill has a second top end higher than the first top end.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Lin SHIH, Chih-Cheng LEE
  • Patent number: 11574911
    Abstract: The present application discloses a method for fabricating a semiconductor device with a protruding contact. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing a top surface of the bit line structure; and forming a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 7, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Chih-Hung Chen, Szu-Yao Chang
  • Patent number: 11569228
    Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 31, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Hsueh-Han Lu, Yu-Ting Lin, Tsang-Po Yang
  • Publication number: 20220384428
    Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Chiang-Lin SHIH, Hsueh-Han LU, Yu-Ting LIN, Tsang-Po YANG
  • Publication number: 20220384352
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Patent number: 11515270
    Abstract: An antenna package includes a conductive layer, an interconnection structure and an antenna. The interconnection structure is disposed on the conductive layer. The interconnection structure includes a conductive via and a first package body. The conductive via has a first surface facing the conductive layer, a second surface opposite to the first surface and a lateral surface extending from the first surface to the second surface. The first package body covers the lateral surface of the conductive via and exposes the first surface and the second surface of the conductive via. The first package body is spaced apart from the conductive layer. The antenna is electrically connected to the second surface of the conductive via.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Lin Shih, Chih-Cheng Lee
  • Patent number: 11469231
    Abstract: The present application discloses a semiconductor device with a protruding contact and a method for fabricating the semiconductor device with the protruding contact. The semiconductor device includes a substrate, a capacitor contact structure protruding from the substrate, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 11, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Chih-Hung Chen, Szu-Yao Chang
  • Patent number: 11456256
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Publication number: 20220293552
    Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
  • Publication number: 20220293561
    Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
  • Publication number: 20220285354
    Abstract: A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Chiang-Lin SHIH, Yu-Ting LIN
  • Patent number: 11374009
    Abstract: A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: June 28, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Yu-Ting Lin
  • Patent number: 11332120
    Abstract: A method of energy management includes steps of: deciding system parameters; determining an object function; obtaining characteristics information and predetermined ranges respectively of the system parameters; calculating function values of the object function for various parameter value combinations of the system parameters within the predetermined ranges based on the characteristics information so as to establish a database; determining a smallest function value among those of the function values in the database that satisfy certain conditions; and determining an optimum power split ratio based on the parameter value combination corresponding to the smallest function value for energy management of the vehicle.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 17, 2022
    Assignee: NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Yi-Hsuan Hung, Syuan-Yi Chen, Kai-Lin Lee, Po-Lin Shih, Tzu-Cheng Chou, Wei-Gang Chen
  • Patent number: 11322216
    Abstract: A fuse array structure includes first and second active areas, first and second line contacts, first and second gate contacts and a common gate layer formed across the first and second active areas. The first line contact and the first gate contact are formed on the first active area. The second line contact and the second gate contact are formed on the second active area. The common gate layer is between the first active area and the first gate contact and is between the second active area and the second gate contact. The first active area, the first line contact, the first gate contact and the common gate layer form a first fuse. The second active area, the second line contact, the second gate contact and the common gate layer form a second fuse.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: May 3, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Chiang-Lin Shih, Hsih-Yang Chiu