Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: The present disclosure discloses a multi-energy coupled cooling/heating system for buildings in a long-term cooling region, including a multi-level management unit for heat sources, a solar energy heat collection unit, a lithium bromide absorptive refrigeration unit, a gas heat complementing unit, a ground source heat pump cooling/heating unit, and an indirect evaporative cooling waste heat recovery unit; the multi-level management unit for heat sources is connected to the solar energy heat collection unit, the lithium bromide absorptive refrigeration unit, the gas heat complementing unit, and the ground source heat pump cooling/heating unit; the ground source heat pump cooling/heating unit is connected to the indirect evaporative cooling waste heat recovery unit. The present disclosure adopts double-water tank structure, designs based on stratification principle, so as to achieve heat source classification management.

Abstract: Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.

Abstract: A semiconductor device including a substrate, a magnetic core and a conductor coil is provided. The magnetic core is disposed on the substrate, and formed by sub-layers of different materials stacked alternatively on one another. The conductor coil is disposed on the substrate, wherein the magnetic core partially extends to a level between an upper surface of the conductor coil and a bottom surface of the conductor coil.

Abstract: A lightweight table structure includes a frame having a quadrilateral shape, a top panel mounted on a top of the frame, a bottom panel mounted on a bottom of the frame, and a decorative laminate sheet mounted on the top panel by a laminating process. The frame has a hollow interior. The frame includes a front panel, a rear panel, a left panel, and a right panel which are combined together. The frame further includes multiple reinforcing ribs and multiple reinforcing plates mounted between the front panel, the rear panel, the left panel, and the right panel. The reinforcing ribs are spaced and arranged in parallel. The reinforcing plates are spaced and arranged in parallel.

Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.

Abstract: A display panel and a display device are provided. An organic light-emitting layer includes a doped region and an undoped region, and the undoped region is located between the doped region and the hole blocking layer. When the display panel is in a low grayscale display state, an exciton concentration distribution curve of the organic light-emitting layer includes a first peak located in the doped region and a second peak located in the undoped region, and a peak value of the second peak is less than a peak value of the first peak.

Abstract: An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.

Abstract: A display device includes a button, a first data transmission port, a second data transmission port, a first image transmission port, a second image transmission port, and a microcontroller. The first data transmission port is coupled to a first electronic device. The second data transmission port is coupled to a second electronic device. The first image transmission port is coupled to the first electronic device. The second image transmission port is coupled to the second electronic device. The microcontroller selects the first image transmission port, the second image transmission port, or both to generate a video signal. When the button is pressed, if the microcontroller selects the first image transmission port, the microcontroller switches the first data transmission port to the second data transmission port, and receives image-transmission-port information stored in the second electronic device through the second data transmission port.

Abstract: An improved integrated coil structure includes an iron core body and first, second, third, and fourth coils. The iron core body includes first and second wire-winding portions. The iron core body is provided with first and second flanges respectively at two sides thereof and a third flange arranged between the first and second flanges. First and second electrodes are arranged on the first flange. Third and fourth electrodes are arranged on the second flange. Fifth, sixth, and seventh electrodes are arranged on the third flange. Two terminals of the first coil are electrically connected with the first and fifth electrodes. Two terminals of the second coil are electrically connected with the second and seventh electrodes. Two terminals of the third coil are electrically connected with the third and sixth electrodes. Two terminals of the fourth coil are electrically connected with the fourth and seventh electrodes.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: An antenna-in-package with a heat dissipation structure includes a circuit board, an antenna substrate, a chip, a plurality of heat dissipation fins, a chassis, and dielectric fluid. The circuit board has a first surface and a second surface opposite to the first surface. The antenna substrate is disposed above the first surface of the circuit board. The chip is disposed between the antenna substrate and the first surface of the circuit board and is electrically connected to the antenna substrate. The plurality of heat dissipation fins protrude from the second surface of the circuit board. The chassis encapsulates the circuit board, the antenna substrate, the chip, and the plurality of heat dissipation fins. The dielectric fluid circulates and flows in the chassis through a cooling circulation device and is in direct contact with the plurality of heat dissipation fins.

Abstract: Various solutions for enhancing quality of service (QoS) based on environmental conservation in mobile communications are described. An apparatus may determine whether an eco-friendly condition associated with a data session is met. Also, the apparatus may determine to modify a QoS associated with the data session in an event that the eco-friendly condition associated with the data session is met.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: An optoelectronic module, including a substrate, a covering member, a light emitting element, and a light receiving element, is provided. The covering member is disposed on the substrate and includes an upper cover portion, a peripheral sidewall portion connected to the upper cover portion, and an inside partition delimiting a first cavity and a second cavity. The first cavity is separated from the second cavity. The light emitting element is disposed on the substrate as corresponding to the first cavity. The light receiving element is disposed on the substrate as corresponding to the second cavity. The inside partition has a first inner wall surface located in the first cavity and a second inner wall surface located in the second cavity. A first protruded-recessed structure is formed on the first inner wall surface.