Abstract: Interaction is created between users and streamers even when the users give gifts to the streamers outside live-streams. Provided is a terminal of a user, which includes: one or more processors; and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: receiving, from the user, an instruction to use a gift for a streamer while the user is not participating in a live-stream of the streamer; and causing an output unit to output an effect corresponding to the use of the gift by the user while the streamer is live-streaming.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

Abstract: A manufacturing method of an elastic paint is provided. The manufacturing method includes: blending an original composition to produce a first rough painting material, where the original composition includes polycarbonatediol (PCDL), a polyurethane (PU) elastic powder, poly(methyl methacrylate) (PMMA), a photoinitiator, a wetting agent, a solvent, and an auxiliary agent; carrying out precipitation treatment on the first rough painting material, and filtering the treated first rough painting material, to produce a second rough painting material; blending the second rough painting material; sealing the blended second rough painting material to produce a plurality of layers in the second rough painting material; removing an upper portion and a lower portion from the layers to produce a main ingredient; and adding a curing agent and a diluent into the main ingredient to produce an elastic paint.

Abstract: This disclosure provides methods, devices and systems for increasing carrier frequencies for wireless communications in wireless local area networks (WLANs). Some implementations more specifically relate to packet designs that support wireless communications on carrier frequencies above 7 GHz. In some aspects, a wireless communication device may map a physical layer convergence protocol (PLCP) protocol data unit (PPDU) to orthogonal subcarriers according to existing tone plans associated with carrier frequencies below 7 GHz and may up-clock the PPDU for transmission on carrier frequencies above 7 GHz (such as by increasing the frequency of a clock signal used to convert the PPDU between the frequency domain and the time domain). In some implementations, the PPDU may conform to an existing PPDU format designed for sub-7 GHz wireless communications. In some other implementations, the PPDU may conform to a “green field” PPDU format optimized for wireless communications on carrier frequencies above 7 GHz.

Abstract: A method of forming an integrated circuit includes forming at least a first or a second set of devices in a substrate, forming an interconnect structure over the first or second set of devices, and depositing a set of conductive structures on the interconnect structure. The first and second set of devices are configured to operate on a first supply voltage. Forming the interconnect structure includes depositing a set of insulating layers over the first or second set of devices, etching the set of insulating layers thereby forming a set of trenches, depositing a conductive material within the set of trenches, thereby forming a set of metal layers, and forming a portion of a header circuit between a first and a second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers, two epitaxial structures, a conductive structure, a via, and a graphene barrier. The channel layers and the epitaxial structures are disposed over the substrate. The channel layers are connected between the epitaxial structures. The conductive structure is disposed on the substrate opposite to the epitaxial structures. The via is connected between one of the epitaxial structure and the conductive structure. The graphene barrier surrounds the via.

Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.

Abstract: A process tube device can detect the presence of any external materials that may reside within a fluid flowing in the tube. The process tube device detects the external materials in-situ which obviates the need for a separate inspection device to inspect the surface of a wafer after applying fluid on the surface of the wafer. The process tube device utilizes at least two methods of detecting the presence of external materials. The first is the direct measurement method in which a light detecting sensor is used. The second is the indirect measurement method in which a sensor utilizing the principles of Doppler shift is used. Here, contrary to the first method that at least partially used reflected or refracted light, the second method uses a Doppler shift sensor to detect the presence of the external material by measuring the velocity of the fluid flowing in the tube.

Abstract: The disclosure provides an application page navigation method and a terminal device. The method includes: obtaining a page navigation relationship diagram; in response to detecting a page navigation request for navigating to a second function page when a first function page is displayed, obtaining a first dimension corresponding to the first function page and a second dimension corresponding to second function page; and determining a page navigation mode corresponding to the page navigation request based on a comparison result of the first dimension and the second dimension.

Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Abstract: An oil and gas fracturing tool is disclosed, mainly involving a fracking tool with an electromagnetic intelligent control sliding sleeve including an outer sleeve section, a dart body section and a control section. The outer sleeve section is at the target location to be fractured. The effect of fracturing is mainly achieved by the dart body, which has an activated state and an inactive state. The initial state is inactive, and the front locking tip can be deformed under pressure during displacement. The diameter can change to pass through any sliding sleeve. When the dart body is counted and is about to reach the fracturing position, the front locking tip is blocked from deformation and cannot be reduced in diameter, thus pressurizing to control the fracturing effect. The control part includes a sensor module, a drive module, a main control module and a power supply module.

Abstract: Disclosed herein relates to a system, comprising: at least one load receiver mounted on a shopping cart or basket and configured to receive an item placed into the shopping cart or basket for a weighing operation; a plurality of sensors configured to detect a plurality of parameters relating to the weighing operation of the item including at least one of: a relative angle between a force sensing axis of the at least one load receiver and a direction of gravity, a motion of the shopping cart or basket, and an ambient temperature surrounding the shopping cart or basket and the at least one load receiver; and a processor configured to determine an actual weight of the item based on at least a portion of the plurality of parameters.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.

Abstract: Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

Abstract: Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.

Abstract: The present disclosure relates to the technical field of solar cell preparation, and provides a solar cell, an AlOx depositing method therefor, and a cell back passivation structure and method. In the present disclosure, a silicon wafer which has been subjected to thermal oxidization and annealing is placed into a tubular PECVD equipment. The chamber is vacuumized to a pressure of 100-2000 mTorr and heated to a temperature of 300-400° C. Then nitrous oxide and TMA as reaction gases are introduced in to the chamber. The radio-frequency power supply is turned on and an AlOx passivation film having two-layer, three-layer, or more-layer film structure is prepared.

Abstract: This disclosure provides methods, devices and systems for increasing carrier frequencies for wireless communications in wireless local area networks. Some implementations more specifically relate to beamforming training operations that support wireless communications on carrier frequencies above 7 GHz. In some aspects, a beamforming initiator may initiate a beamforming training operation by transmitting a number (N) of beamforming training (BFT) packets in N TX beam directions, respectively, on a carrier frequency above 7 GHz. The beamforming responder receives one or more of the BFT packets and provides feedback to the beamforming initiator indicating the TX beam direction associated with the BFT packet having the highest received signal power. In some aspects, the beamforming responder may train its RX antennas for RX beamforming concurrently while the beamforming initiator trains its TX antennas.