Patents by Inventor Lin Yu

Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12283521
    Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 12272621
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kan-Ju Lin, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
  • Patent number: 12272928
    Abstract: An optical transmission module includes a housing having a cavity therein and an optical transmission device encapsulated in the cavity. The optical transmission device includes an optical waveguide substrate, laser assemblies, an optical multiplexing assembly and main waveguides. The optical waveguide substrate includes a surface and a first reflection inclined surface having an acute angle therebetween. The laser assemblies are disposed on the surface of the optical waveguide substrate, and are configured to emit laser beams towards the surface of the optical waveguide substrate. The optical multiplexing assembly is disposed in the optical waveguide substrate, and is configured to combine the laser beams into a laser beam. The main waveguides are disposed inside the optical waveguide substrate, light inlet ends of the main waveguides face the first inclined surface, and light outlet ends of the main waveguides are communicated with the optical multiplexing assembly.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 8, 2025
    Assignee: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD.
    Inventors: Yi Tang, Jinlei Chen, Feng Cui, Yifan Xie, Qinhao Fu, Lin Yu
  • Patent number: 12266563
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
  • Publication number: 20250107203
    Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12261082
    Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Lin-Yu Huang, Shuen-Shin Liang, Sheng-Tsung Wang, Cheng-Chi Chuang, Chia-Hung Chu, Tzu Pei Chen, Yuting Cheng, Sung-Li Wang
  • Patent number: 12262479
    Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: March 25, 2025
    Assignee: UNEO INC.
    Inventors: Chih-Sheng Hou, Chia-Hung Chou, Hsin-Lin Yu, Si-Wei Chen, Chueh Chiang
  • Patent number: 12255070
    Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsuan Lu, Kan-Ju Lin, Lin-Yu Huang, Sheng-Tsung Wang, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Chih-Hao Wang
  • Patent number: 12255103
    Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20250063824
    Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu HUANG, Shih-Fan CHEN, Sheng-Fu HSU, Yi-An LAI, Chan-Hong CHERN, Cheng-Hsiang HSIEH
  • Patent number: 12205896
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20250021827
    Abstract: A method for finding at least one optimal post-training quantization model includes converting and optimizing a floating-point machine learning model into a converted machine learning model, applying a plurality of PTO settings to generate a plurality of PTO models, and evaluating the plurality of PTO models based on at least one predetermined indirect metric to find at least one optimal PTO model.
    Type: Application
    Filed: June 19, 2024
    Publication date: January 16, 2025
    Applicant: MEDIATEK INC.
    Inventor: Chia-Lin Yu
  • Publication number: 20250015071
    Abstract: Providing a resistor between a gate of a target device (e.g., a gallium nitride (GaN) high-electron-mobility transistor device) and a clamp circuit improves electrostatic discharge (ESD) protection between an input/output (IO) and the target device. For example, the resistor may result in ESD protection between the IO and a source of the target device and between the IO and a drain of the target device may be at least 2 kilovolts under the human body model. Because ESD protection is improved, chances of burn out in the target device are reduced. Additionally, larger currents may be applied in the clamp circuit without risk of ESD.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Inventors: Sheng-Fu HSU, Shih-Fan CHEN, Lin-Yu HUANG
  • Publication number: 20250014993
    Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
    Type: Application
    Filed: September 16, 2024
    Publication date: January 9, 2025
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao WANG
  • Patent number: 12180544
    Abstract: This invention provides novel azido linkers for deoxynucleotide analogues having a detectable marker attached thereto.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 31, 2024
    Inventors: Jingyue Ju, Huanyan Cao, Zengmin Li, Qinglin Meng, Jia Guo, Shenglong Zhang, Lin Yu
  • Publication number: 20240429310
    Abstract: A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Sheng-Fu HSU, Shih-Fan CHEN, Chen-Yi LEE, Pin-Chen CHEN, Lin-Yu HUANG
  • Publication number: 20240415768
    Abstract: A sustained-release gel with insoluble salt as pH adjuster, and its preparation method and application are disclosed. The sustained-release gel is obtained by dissolving polymer in an aqueous solvent, followed by blending and compounding the alkaline inclusion and the insoluble salt crystalline powder. The insoluble salt is at solid state and thus has thus a large amount as the reservoir of the pH adjuster. The preparation is injectable, can be converted into gel state after being injected into organism, and realizes the sustained release of the inclusion at the injection site. The presence of the insoluble salt reduces the solubility of the inclusion in the gel by releasing the free salt sustainably and thus adjusting the pH inside the gel in a sustained manner. The burst release of the inclusion out of the gel is significantly alleviated.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 19, 2024
    Inventors: JIANDONG DING, WEN GUO, DINGLINGGE CAO, LIN YU
  • Patent number: 12166092
    Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240406072
    Abstract: At a topology controller, a method may: receive a topology request at the topology controller, based at least partially on the topology request, select an input-output (I/O) link connecting an input node to a destination node from a plurality of I/O links including at least: a direct I/O link between the input node and the destination node, and a switched I/O link between the input node and the destination node, and configure an active I/O link between the input node and the destination node based on the selected I/O link.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Nitin BHARDWAJ, James Jui-Lin YU
  • Publication number: 20240404882
    Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.
    Type: Application
    Filed: May 27, 2024
    Publication date: December 5, 2024
    Inventors: Sheng-Tsung WANG, Chia-Hao CHANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG