Patents by Inventor Lin Yu

Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220150055
    Abstract: In some examples, for process-to-process communication, such as in function linking, a virtual channel can be provisioned to provide virtual machine to virtual machine communications. In response to a transmit request from a source virtual machine, the virtual channel can cause a data copy from a source buffer associated with the source virtual machine without decryption or encryption. The virtual channel provisions a key identifier for the copied data. The destination virtual machine can receive an indication data is available and can cause the data to be decrypted using a key accessed using the key identifier and source address of the copied data. In addition, the data can be encrypted using a second, different key for storage in a destination buffer associated with the destination virtual machine. In some examples, the key identifier and source address is managed by the virtual channel and is not visible to virtual machine or hypervisor.
    Type: Application
    Filed: April 19, 2019
    Publication date: May 12, 2022
    Inventors: Bo CUI, Cunming LIANG, Jr-Shian TSAI, Ping YU, Xiaobing QIAN, Xuekun HU, Lin LUO, Shravan NAGRAJ, Xiaowen ZHANG, Mesut A. ERGIN, Tsung-Yuan C. TAI, Andrew J. HERDRICH
  • Publication number: 20220146249
    Abstract: A grating displacement measuring device based on conical diffraction, including a laser diode configured to emit a measuring beam, a collimating lens, a polarizing beam splitter, a first reflecting mirror, a second reflecting mirror, a third reflecting mirror, a fourth reflecting mirror and a phase shift measuring unit. A grating displacement measuring method based on conical diffraction is also provided.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Inventors: Wenhao LI, Zhaowu LIU, Wei WANG, Lin LIU, Shan JIANG, Hongzhu YU, Yanxiu JIANG
  • Patent number: 11328990
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a first metal via passing through the first insulating layer, and a second insulating layer formed over the first insulating layer. The semiconductor device structure also includes a first metal hump surrounded by the second insulating layer and connected to the top surface of the first metal via. The first metal hump covers the portion of the first insulating layer adjacent to the first metal via. In addition, the semiconductor device structure includes a metal line formed in the second insulating layer and electrically connected to the first metal via, and a conductive liner covering the first metal hump and separating the metal line from the second insulating layer and the first metal hump.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11320583
    Abstract: A backlight module comprises a frame unit, a plurality of light-emitting units, a first optical unit and a second optical unit. The frame unit includes a metal rear frame. The metal rear frame has a first carrying portion, and a second carrying portion spaced from the first carrying portion. The first carrying portion and the second carrying portion are not at the same height. One of the plurality of light-emitting units is disposed on the first carrying portion, and another one of the plurality of light-emitting units is disposed on the second carrying portion. The first optical unit is configured to receive the light generated from the light-emitting unit disposed on the first carrying portion, and the second optical unit is configured to receive the light generated from the light-emitting unit disposed on the second carrying portion. Through the structure of the metal rear frame, the light-emitting unit can directly contact the metal rear frame and the heat dissipation efficiency can be enhanced.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 3, 2022
    Assignees: RADIANT(GUANGZHOU) OPTO-ELECTRONICS CO, LTD, RADIANT OPTO-ELECTRONICS CORPORATION
    Inventors: Lin-Yu Huang, Yi-Shan Lin, Ching-Chieh Yeh
  • Publication number: 20220130991
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen YU, Huan-Chieh SU, Shih-Chuan CHIU, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Patent number: 11316023
    Abstract: A method includes providing two structures over a substrate and a source/drain (S/D) contact between the structures. Each structure includes a gate, two gate spacers on opposing sidewalls of the gate, and a first capping layer over the gate and the gate spacers. The method further includes recessing the S/D contact to form a trench, in which a top surface of the S/D contact is below a top surface of the gate spacers. The method further includes depositing an inhibitor layer on the S/D contact but not on surfaces of the first capping layer and not on top surfaces of the gate spacers; depositing a liner layer over top and sidewall surfaces of the first capping layer and surfaces of the gate spacers that are exposed in the trench, wherein the liner layer is free from at least a central portion of the inhibitor layer; and removing the inhibitor layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11309212
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220112552
    Abstract: This invention provides novel azido linkers for deoxynucleotide analogues having a detectable marker attached thereto.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Jingyue Ju, Huanyan Cao, Zengmin Li, Qinglin Meng, Jia Guo, Shenglong Zhang, Lin Yu
  • Publication number: 20220115510
    Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.
    Type: Application
    Filed: October 13, 2020
    Publication date: April 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen YU, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Lin-Yu Huang
  • Patent number: 11302798
    Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chi Chuang, Lin-Yu Huang, Chia-Hao Chang, Yu-Ming Lin, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Publication number: 20220093448
    Abstract: An integrated circuit (IC) structure includes a transistor, a front-side interconnection structure, a backside via, and a backside interconnection structure. The transistor includes a source/drain epitaxial structure. The front-side interconnection structure is on a front-side of the transistor. The backside via is connected to the source/drain epitaxial structure of the transistor. The backside interconnection structure is connected to the backside via and includes a conductive feature, a dielectric layer, and a spacer structure. The conductive feature is connected to the backside via. The dielectric layer laterally surrounds the conductive feature. The spacer structure is between the conductive feature and the dielectric layer and has an air gap.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 24, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen YU, Huan-Chieh SU, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Patent number: 11281523
    Abstract: A system for poisoned data management includes an interface and a processor. The interface is configured to receive an indication for remediation of poisoned data. The processor is configured to correct the poisoned data associated with an event in a storage location, wherein the storage location is determined based at least in part on a data graph associated with the poisoned data, and wherein the data graph is determined based at least in part on the data sourcing information of a published event associated with the poisoned data.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 22, 2022
    Assignee: Ridgeline, Inc.
    Inventors: Timophey Zaitsev, Charles Chang-Lin Yu
  • Publication number: 20220075528
    Abstract: A storage system and an access control method thereof are provided. The storage system receives a first I/O request from at least one hypervisor. The first I/O request is used for accessing a first disk file of disk files. The storage system then operates a first I/O operation of a first virtual disk of virtual disks according to the first I/O request since the disk files correspond to the virtual disks. The storage system reads a QoS data of the first disk file and determines a first delay period according to the QoS data. The storage system transmits a first I/O response to the at least one hypervisor after the first delay period.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Applicant: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Kuan-Kai Chiu, Tsung-Lin Yu
  • Publication number: 20220069076
    Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the via.
    Type: Application
    Filed: January 27, 2021
    Publication date: March 3, 2022
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20220069117
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 3, 2022
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11264326
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Kuan-Lun Cheng, Chih-Hao Wang, Cheng-Chi Chuang, Chia-Hao Chang
  • Patent number: 11257926
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11257758
    Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20220052167
    Abstract: A device includes a substrate, a gate structure over the substrate, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer, wherein a bottom surface of the dielectric liner is spaced away from the silicide by a gap, and an S/D contact over the silicide and at least partially filling the gap.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 17, 2022
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11249670
    Abstract: The present invention provides a sever which includes a network interface, a processor and a first storage device, wherein the processor is arranged for communicating with an electronic device via the network interface, and the first storage device stores data. In the operations of the server, the processor determines whether the data is cold data; and when the data is determined as the cold data, the processor moves a second portion of the data to a second storage device, and a first portion of the data is remained in the first storage device, wherein the data amount of the first portion is less than data amount of the second portion, and the access speed of the first storage device is higher than the access speed of the second storage device.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: February 15, 2022
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Tsung-Lin Yu, Cheng-Yue Chang, Po-Hsun Yen