Patents by Inventor Lin Yu
Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12389670Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.Type: GrantFiled: January 23, 2023Date of Patent: August 12, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
-
Patent number: 12389665Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.Type: GrantFiled: January 11, 2024Date of Patent: August 12, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
-
Publication number: 20250254907Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.Type: ApplicationFiled: April 23, 2025Publication date: August 7, 2025Inventors: Kan-Ju Lin, Chien Chang, Chih-Shiun Chou, TaiMin Chang, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Lin-Yu Huang
-
Publication number: 20250245495Abstract: A data processing method for quantization, includes the following steps. A first set of models are loaded. The first set of models are quantized based on a unified quantization parameter to obtain a first set of quantized models. The first set of models include at least one model, the first set of quantized models include at least one quantized model, and the unified quantization parameter is obtained according to several quantization parameters of a second set of models.Type: ApplicationFiled: January 16, 2025Publication date: July 31, 2025Inventors: Chun-Chen Lin, Chia-Da Lee, Chia-Lin Yu, Jia-Ren Chang, Chih-Wen Goo, Chih-Wei Chen
-
Publication number: 20250246480Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.Type: ApplicationFiled: March 21, 2025Publication date: July 31, 2025Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
-
Publication number: 20250246903Abstract: The present disclosure provides a semiconductor device, which includes a control circuit, a driving circuit, a voltage pull-up device, and a discharging circuit. The control circuit is coupled between a first terminal and a second terminal of the integrated circuit, and provides a first voltage at a first node. The driving circuit is electrically connected to the control circuit at the first node, and provides a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal. The voltage pull-up device is coupled between the first terminal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal. The discharging circuit is electrically connected to the second node, and coupled between the first terminal and the second terminal.Type: ApplicationFiled: January 25, 2024Publication date: July 31, 2025Inventors: SHENG-FU HSU, SHIH-FAN CHEN, LIN-YU HUANG
-
Patent number: 12369365Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.Type: GrantFiled: March 1, 2024Date of Patent: July 22, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
-
Patent number: 12363939Abstract: A semiconductor device structure includes a source/drain (S/D) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a first silicide layer in contact with the first surface of the S/D feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the S/D feature, a front side S/D contact in contact with the first silicide layer, a back side S/D contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ILD) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ILD and the gate dielectric layer.Type: GrantFiled: March 20, 2024Date of Patent: July 15, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Zhen Yu, Shih-Chuan Chiu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su
-
Patent number: 12363946Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.Type: GrantFiled: May 6, 2024Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
-
Publication number: 20250226291Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.Type: ApplicationFiled: March 24, 2025Publication date: July 10, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kan-Ju LIN, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
-
Patent number: 12356688Abstract: A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.Type: GrantFiled: June 27, 2022Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Tsung Wang, Huan-Chieh Su, Chun-Yuan Chen, Lin-Yu Huang, Min-Hsuan Lu, Chih-Hao Wang
-
Patent number: 12352880Abstract: A spatial positioning method is provided. The method includes steps of: dividing an activity space into a plurality of activity regions; selecting a plurality of positions in the activity space or within a distance range of the activity space as a plurality of base station candidate positions; predicting connection states between the plurality of base stations that are disposed respectively at the plurality of station candidate positions and a mobile robot moving to each of the plurality of activity regions; selecting some of the base station candidate positions as a plurality of base station positions according to the connection states; disposing the plurality of base stations respectively at the plurality of base station positions; and wirelessly connecting the mobile robot respectively moving to the plurality of activity regions to some of the plurality of base stations to position the mobile robot.Type: GrantFiled: January 29, 2023Date of Patent: July 8, 2025Assignee: PSJ INTERNATIONAL LTD.Inventors: Tzu-Yi Yang, Meng-Lin Yu, Ju-Chin Chao, Ruey-Beei Wu
-
Patent number: 12347748Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.Type: GrantFiled: August 19, 2022Date of Patent: July 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Bo Liao, Chun-Yuan Chen, Lin-Yu Huang, Yi-Hsun Chiu, Chih-Hao Wang
-
Patent number: 12336215Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The semiconductor device structure includes a first source/drain (S/D) structure formed adjacent to the gate structure, and a first S/D contact structure formed over the first S/D structure. The semiconductor device structure includes a first filling layer formed over the first S/D structure, and the first S/D contact structure is surrounded by the first filling layer. The semiconductor device structure includes a dielectric layer formed adjacent to the gate structure and the first filling layer, and the dielectric layer and the first filling layer are made of different materials. The first filling layer is surrounded by the dielectric layer.Type: GrantFiled: September 8, 2021Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Li-Zhen Yu, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
-
Publication number: 20250183040Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.Type: ApplicationFiled: February 12, 2025Publication date: June 5, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min-Hsuan LU, Kan-Ju LIN, Lin-Yu HUANG, Sheng-Tsung WANG, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI, Chih-Hao WANG
-
Patent number: 12324188Abstract: A device includes a substrate and a gate structure wrapping around at least one vertical stack of nanostructure channels. The device includes a source/drain region abutting the gate structure, and a source/drain contact over the source/drain region. The device includes an etch stop layer laterally between the source/drain contact and the gate structure and having a first sidewall in contact with the source/drain contact, and a second sidewall opposite the first sidewall. The device includes a source/drain contact isolation structure embedded in the source/drain contact and having a third sidewall substantially coplanar with the second sidewall of the etch stop layer.Type: GrantFiled: September 23, 2021Date of Patent: June 3, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
-
Patent number: 12324182Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.Type: GrantFiled: May 5, 2023Date of Patent: June 3, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Li-Zhen Yu, Chia-Hao Chang, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
-
Publication number: 20250167140Abstract: A semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit in a top view of the semiconductor device. At least one guard ring of the one or more guard rings includes an active region in the substrate, a first plurality of elongated conductive structures extending in a first direction in the top view of the semiconductor device and arranged in a second direction in the top view of the semiconductor device, and a second plurality of elongated conductive structures extending in the second direction and arranged in the first direction. The combination of the first and second pluralities of elongated conductive structures forms a conductive grid above the active region, and provides increased coverage of the surface area of the active region relative to including only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures.Type: ApplicationFiled: February 15, 2024Publication date: May 22, 2025Inventors: Lin-Yu HUANG, Shih-Fan CHEN, Sheng-Fu HSU
-
Publication number: 20250167117Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.Type: ApplicationFiled: January 17, 2025Publication date: May 22, 2025Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
-
Patent number: 12302607Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.Type: GrantFiled: May 21, 2024Date of Patent: May 13, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang