Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. A backside power rail is included.

Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. A first recess cavity is formed over a gate electrode, and a second recess cavity is formed over the epitaxial semiconductor material portion. The second recess cavity is vertically recessed to form a connector via cavity. A metallic cap structure is formed on the gate electrode in the first recess cavity, and a connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A method for estimating a voltage support strength of a renewable energy grid-connected power system. A first short-circuit ratio index of a renewable energy grid-connected power system is determined based on a short-circuit capacity provided for a grid connection point by an alternating-current system, An equivalent grid connection capacity of renewable energy at the grid connection point is determined. A second short-circuit ratio index of the renewable energy grid-connected power system is determined based on a voltage variation at a position where the renewable energy is connected to the grid connection point. A critical short-circuit ratio of the renewable energy grid-connected power system determined based on a parameter of the alternating-current system and an equivalent maximum transmission power.

Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.

Abstract: Direct memory access data path for RAID storage is disclosed, including: receiving, at a Redundant Array of Independent Disks (RAID) controller, a request to write data to be distributed among a plurality of storage devices; computing parity information based at least in part on the data associated with the request; causing the parity information to be stored on a first subset of the plurality of storage devices; and causing the data associated with the request to be stored on a second subset of the plurality of storage devices, wherein the plurality of storage devices is configured to obtain the data associated with the request directly from a memory that is remote to the RAID controller, and wherein the data associated with the request does not pass through the RAID controller.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

Abstract: Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.

Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.