Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate and a gate electrode overlying the substrate. Further, the integrated chip includes a contact layer overlies the substrate and is laterally spaced apart from the gate electrode by a spacer structure. The spacer structure may surround outermost sidewalls of the gate electrode. A hard mask structure may be arranged over the gate electrode and between portions of the spacer structure. A contact via extends through the hard mask structure and contacts the gate electrode. The integrated chip may further include a liner layer that is arranged directly between the hard mask structure and the spacer structure, wherein the liner layer is spaced apart from the gate electrode.

Abstract: The present invention provides a wirelessly connected manicure machine, which includes a housing, a control module, an input interface and a wireless communication module. The housing has an internal cavity, an opening corresponding to one side of the internal cavity, and one or more ultraviolet light emitting diode (UV LED) modules provided in the internal cavity. The input interface is connected to the control module to input a corresponding trigger instruction to the control module. The control module is connected to the UV LED module. The control module is also connected to the wireless communication module to send and receive signals through the wireless communication module.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.

Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.

Abstract: A unidirectional transmission device includes at least one substrate, at least one light source, and at least one light-sensing element. The at least one substrate includes at least one recess. The at least one light source is configured to transform an electrical signal into an optical signal, and transmit the optical signal. The at least one light-sensing element is configured to receive the optical signal, and transform the optical signal into the electrical signal, wherein the at least one recess is configured to dispose the at least one light source, or configured to dispose the at least one light-sensing element, or configured to reflect the optical signal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a first upper portion of the fin. The semiconductor device structure includes a first stressor and a second stressor respectively over opposite first sides of the fin. The semiconductor device structure includes a spacer structure between the gate stack and the first stressor. The semiconductor device structure includes a first spacer layer covering a sidewall of the gate stack, the spacer structure, and the first stressor. The semiconductor device structure includes a dielectric layer over the first spacer layer. The semiconductor device structure includes an etch stop layer between the first spacer layer and the dielectric layer. The semiconductor device structure includes a seal structure between the second upper portion and the third upper portion.

Abstract: A device and a method for virtual storage are provided. The device includes a physical processor, a hypervisor and a physical storage. The hypervisor is executed on the physical processor and configured to create at least one client virtual machine and a controller virtual machine. The physical storage is clustered with physical storage of at least another device via the controller virtual machine to form a storage cluster. The controller virtual machine is further configured to define a virtual storage pool in the storage cluster and create at least one virtual storage controller virtual machine to interface the at least one client virtual machine with the virtual storage pool so that the at least one client virtual machine accesses the virtual storage pool via the at least one virtual storage controller virtual machine and the controller virtual machine. The method is applied to the device to implement the operations.

Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.

Abstract: An optical transmission module includes a housing having a cavity therein and an optical transmission device encapsulated in the cavity. The optical transmission device includes an optical waveguide substrate, laser assemblies, an optical multiplexing assembly and main waveguides. The optical waveguide substrate includes a surface and a first reflection inclined surface having an acute angle therebetween. The laser assemblies are disposed on the surface of the optical waveguide substrate, and are configured to emit laser beams towards the surface of the optical waveguide substrate. The optical multiplexing assembly is disposed in the optical waveguide substrate, and is configured to combine the laser beams into a laser beam. The main waveguides are disposed inside the optical waveguide substrate, light inlet ends of the main waveguides face the first inclined surface, and light outlet ends of the main waveguides are communicated with the optical multiplexing assembly.

Abstract: A liveness detection device comprising a light source unit, image sensor unit, and data processing module and authentication method thereof are provided. The light source unit comprises a substrate having a first inclined surface, whereby emitted light is reflected light from the first inclined surface. An application triggers an authentication process, which is indicated to a user. The light source unit begins illumination having a specific pattern and for a specific period and image signals are generated. Liveness detection signals are generated, via calculation of interference patterns, each, from more than one image signal, in sequence, for determination of liveness. When a liveness threshold is met, feature recognition data is generated, via calculation of interference patterns, each, from more than one image signal, in sequence, for matching. Then, the features are compared with previously enrolled data for locking or unlocking of the liveness detection device and/or system coupled thereto.

Abstract: A computer-implemented process for controlling a vehicle interior includes detecting a previously defined situation that relates to an undesirable environmental condition of the vehicle interior, and assessing both a risk level and an urgency level, based on a vehicle sensor input. The process also includes generating a vehicle command based upon the detected previously defined situation, the assessed risk level, and assessed urgency level, and executing the generated vehicle command to control at least one of an engine, a window, and a heating, ventilation and air conditioning (HVAC) unit to modify an environmental condition of the vehicle interior.

Abstract: A data transmission and protection system includes a plurality of solid-state drives (SSDs), a storage medium, a central processing unit (CPU) and a massively parallel processor (MPP). The storage medium storing an application program and a redundant array of independent disks (RAID) configuration. The CPU is coupled to the storage medium and configured to execute the application program to generate a virtual SSD interface for the plurality of SSDs according to the RAID configuration. The MPP is coupled to the virtual SSD interface and the plurality of SSDs. The MPP is configured to execute data exchange with the plurality of SSDs in response to a command received from the virtual SSD interface.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: An image transmission system is disclosed. The image transmission system includes at least one image capturing device, at least one conversion device, at least one image processor, and at least one flexible printed circuit (FPC). The at least one FPC includes at least one conductive layer and at least one optical waveguide layer. The at least one image capturing device is configured to capture at least one data. The at least one conversion device is configured to perform a conversion between the at least one data and an optical signal. The at least one image processor is configured to obtain the at least one data according to the optical signal, and processes the data. The at least one optical waveguide layer is configured to transmit the optical signal.

Abstract: The present disclosure describes a method for forming an interconnect structure. The method can include forming a first layer of insulating material on a substrate, forming a via recess within the layer of insulating material, filling the via recess with a layer of conductive material, selectively growing a second layer of insulating material over the first layer of insulating material, and opening the second layer of insulating material to the layer of conductive material while growing the second layer of insulating material.

Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

Abstract: A backlight module comprises a frame unit, a plurality of light-emitting units, a first optical unit and a second optical unit. The frame unit includes a metal rear frame. The metal rear frame has a first carrying portion, and a second carrying portion spaced from the first carrying portion. The first carrying portion and the second carrying portion are not at the same height. One of the plurality of light-emitting units is disposed on the first carrying portion, and another one of the plurality of light-emitting units is disposed on the second carrying portion. The first optical unit is configured to receive the light generated from the light-emitting unit disposed on the first carrying portion, and the second optical unit is configured to receive the light generated from the light-emitting unit disposed on the second carrying portion. Through the structure of the metal rear frame, the light-emitting unit can directly contact the metal rear frame and the heat dissipation efficiency can be enhanced.