Patents by Inventor Lin Yu

Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210126129
    Abstract: A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a cap layer formed over the gate structure. The structure also includes a contact structure formed over the gate structure penetrating through the cap layer. The structure also includes an isolation film formed over sidewalls of the contact structure. The isolation film is separated from the gate structure, and a bottom surface of the isolation film is below a top surface of the cap layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu HUANG, Li-Zhen YU, Chia-Hao CHANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
  • SEMICONDUCTOR STRUCTURE WITH A LAMINATED LAYER
    Publication number: 20210118731
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • VIA STRUCTURE HAVING LOW INTERFACE RESISTANCE AND METHOD FOR FORMING THE SAME
    Publication number: 20210098368
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a first metal via passing through the first insulating layer, and a second insulating layer formed over the first insulating layer. The semiconductor device structure also includes a first metal hump surrounded by the second insulating layer and connected to the top surface of the first metal via. The first metal hump covers the portion of the first insulating layer adjacent to the first metal via. In addition, the semiconductor device structure includes a metal line formed in the second insulating layer and electrically connected to the first metal via, and a conductive liner covering the first metal hump and separating the metal line from the second insulating layer and the first metal hump.
    Type: Application
    Filed: April 22, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen YU, Lin-Yu HUANG, Cheng-Chi CHUANG, Yu-Ming LIN, Chih-Hao WANG
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210098307
    Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Lin-Yu HUANG, Sheng-Tsung WANG, Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • USE OF HYDROGEL COMPOSITION FOR ALLEVIATING DEGENERATIVE JOINT AND TENDON TEAR
    Publication number: 20210085606
    Abstract: The disclosure provides a use of hydrogel composition for alleviating degenerative joint and tendon tear. The hydrogel composition includes 100 parts by weight of therapeutic agent and 120-380 parts by weight of biodegradable copolymer, wherein the therapeutic agent comprises platelet-rich plasma (PRP), doxorubicin, transforming growth factor, bovine serum albumin, or a combination thereof. The biodegradable copolymer has a structure of Formula (I) or Formula (II): wherein A is a hydrophilic polyethylene glycol polymer; B is a hydrophobic polyester polymer; BOX is a bifunctional group monomer of 2, 2?-bis(2-oxazoline) used for coupling the blocks A-B or B-A-B; and n is 0 or an integer greater than 0.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Wen-Shiang CHEN, Chueh-Hung WU, Ming-Kuan SUN, Yu-Chi WANG, Sen-Lu CHEN, Wei-Lin YU, Lih-Tao HSU, Shih-Ping LIN
  • GATE SPACER WITH AIR GAP FOR SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210083067
    Abstract: A semiconductor device structure includes a gate stack and an adjacent source/drain contact structure formed over a semiconductor substrate. The semiconductor device structure includes a first gate spacer structure extending from a sidewall of the gate stack to a sidewall of the source/drain contact structure, and a second gate spacer structure formed over the first gate spacer structure and between the gate stack and the source/drain contact structure. The second gate spacer structure includes first and second gate spacer layers adjacent to the sidewall of the gate stack and the sidewall of the source/drain contact structure, respectively, and a third gate spacer layer separating the first gate spacer layer from the second gate spacer layer, so that an air gap is sealed by the first, second, and the third gate spacer layers and the first gate spacer structure.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Sheng-Tsung Wang, Lin-Yu Huang, Chia-Lin Chuang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Fixing device for blood vessel suturing
    Patent number: 10945736
    Abstract: A fixing device for suturing of blood vessels is provided, which includes a connecting rod, a first clamping member, a second clamping member, a first extension tube and a second extension tube. One end of the first clamping member is disposed on the connecting rod, and the other end of the first clamping member has a first clamping head. One end of the second clamping member is disposed on the connecting rod, and the other end of the second clamping member has a second clamping head. The first extension tube is disposed on an inner side of the first clamping head. The second extension tube is disposed on an inner side of the second clamping head and opposite to the first extension tube, wherein a relative position of the first extension tube and the second extension tube is adjustable.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 16, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wan-Shiun Lou, Yuen-Yung Loh, Yung-Lung Liu, Wei-Lin Yu, Yen-Ling Wang, Hsin-Hsin Shen, Chia-Hao Chang
  • Slow-start photocuring device and switch control module thereof
    Patent number: 10946413
    Abstract: The present invention provides a slow-start photocuring device, comprising: a housing, an ultraviolet (UV) light-emitting diode (LED) module, and a switch control module. The housing has an inner side provided with an internal cavity, wherein the inner side of the housing is further provided with one or a plurality of openings on one or two sides of the internal cavity. The UV LED module is provided around the internal cavity, wherein the UV LED module has a light-emitting side facing the internal cavity. The switch control module is connected to the UV LED module, wherein the switch control module includes a signal modulator, the signal modulator activates a buffer mode when receiving a trigger signal, and the UV LED module in the buffer mode outputs light of a plurality of brightness levels sequentially according to an output signal of the signal modulator.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 16, 2021
    Assignee: COSMEX CO. LTD.
    Inventors: Wan Chieh Hsieh, Hao-Hong Ciou, Lin-Yu Sia, Chun Ching Liu
  • EYEGLASS LENS PROCESSING APPARATUS CALIBRATING METHOD
    Publication number: 20210069852
    Abstract: An eyeglass lens processing apparatus calibrating method is disclosed. The eyeglass lens processing apparatus includes an optical encoder. The eyeglass lens processing apparatus calibrating method includes steps of: (a) when a first object and a second object approach each other, using the optical encoder cooperated with an algorithm to detect whether the first object and the second object touch each other; (b) if a detection result of the step (a) is yes, ending detection immediately and feedbacking a trigger signal; and (c) calibrating a parameter of the eyeglass lens processing apparatus to a calibrated value according to the trigger signal.
    Type: Application
    Filed: September 4, 2020
    Publication date: March 11, 2021
    Inventors: Chun-Lin YU, Ching-Hung LIN
  • Slot contacts and method forming same
    Patent number: 10943829
    Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • STRUCTURE AND METHOD FOR BI-LAYER SELF-ALIGNED CONTACT
    Publication number: 20210066470
    Abstract: The present disclosure provides embodiments of a semiconductor structure having bi-layer self-aligned contact. The semiconductor structure includes a gate stack disposed on a semiconductor substrate and having a first height, a spacer disposed on a sidewall of the gate stack and having a second height greater than the first height, and a first etch stop layer disposed on a sidewall of the gate spacer and having a third height greater than the second height. The semiconductor structure further includes a first dielectric layer disposed over the gate stack and contacting the gate spacer and the first etch stop layer and a second dielectric layer disposed on the first dielectric layer and contacting the first etch stop layer.
    Type: Application
    Filed: June 8, 2020
    Publication date: March 4, 2021
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Gate spacer with air gap for semiconductor device structure and method for forming the same
    Patent number: 10937884
    Abstract: A semiconductor device structure includes a gate stack and an adjacent source/drain contact structure formed over a semiconductor substrate. The semiconductor device structure includes a first gate spacer structure extending from a sidewall of the gate stack to a sidewall of the source/drain contact structure, and a second gate spacer structure formed over the first gate spacer structure and between the gate stack and the source/drain contact structure. The second gate spacer structure includes first and second gate spacer layers adjacent to the sidewall of the gate stack and the sidewall of the source/drain contact structure, respectively, and a third gate spacer layer separating the first gate spacer layer from the second gate spacer layer, so that an air gap is sealed by the first, second, and the third gate spacer layers and the first gate spacer structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Tsung Wang, Lin-Yu Huang, Chia-Lin Chuang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD
    Publication number: 20210057285
    Abstract: A method includes forming a first dummy gate and a second dummy gate over a fin that protrudes above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first and the second metal gates, the dielectric cut pattern extending further from the substrate than the first and the second metal gates; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern underlying the opening; filling the opening with a first electrically conductive material; and recessing the first electrically conductive material below an upper surface of the dielectric cut pattern.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210057569
    Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu HUANG, Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Pluggable printed circuit board and optical module having a gap between solder resist and electro-conductive contact sheet group
    Patent number: 10912200
    Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive contact sheet group positioned on the surface of the substrate, where a part of the substrate is overlaid with solder resist, and there is a gap between the solder resist and the electro-conductive contact sheet group.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 2, 2021
    Assignees: Hisense Broadband Multimedia Technologies Co., Ltd., Hisense USA Corporation, Hisense International Co., Ltd.
    Inventors: Wei Zhao, Wei Cui, Lin Yu
  • COMPOSITION FOR TREATING BRAIN STROKE
    Publication number: 20210023157
    Abstract: The present invention provides a method for treating brain stroke, including: administering to a subject in need a composition, including: an extract of a mixture, wherein the mixture includes Chuanxiong Rhizoma, Rhei Radix et Rhizoma, Angelicae Dahuricae Radix, Scutellaria baicalensis, Coptidis Rhizoma, Gardeniae Fructus, and Carica papaya.
    Type: Application
    Filed: July 23, 2019
    Publication date: January 28, 2021
    Inventors: Jaan-Yih TSAI, Lin-Yu TSAI, Yih-Chih TSAI
  • TRICYCLE-FRAME ADJUSTMENT STRUCTURE
    Publication number: 20210016853
    Abstract: The main structure of the present invention comprises: a carrying-frame set with a cargo-carrying structure, direction-guiding wheels, and a connection component comprising a sleeving-connection element and a quick-dismantling component; wherein the connection component is provided for connecting a power-providing frame set with an adjustment component comprising an assembly-connection element and a connection portion, and a steering component is set at the side of the connection component. Thereby, the user can adjust the distance between the carrying-frame and the power-providing frame to achieve the advantage of saving the accommodation space through the steering component.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventor: Ping-Lin Yu
  • Composition for treating brain stroke
    Patent number: 10888597
    Abstract: The present invention provides a method for treating brain stroke, including: administering to a subject in need a composition, including: an extract of a mixture, wherein the mixture includes Chuanxiong Rhizoma, Rhei Radix et Rhizoma, Angelicae Dahuricae Radix, Scutellaria baicalensis, Coptidis Rhizoma, Gardeniae Fructus, and Carica papaya.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 12, 2021
    Assignee: ENLIVEN BIOTECHNOLOGY CO, LTD.
    Inventors: Jaan-Yih Tsai, Lin-Yu Tsai, Yih-Chih Tsai
  • SEMICONDUCTOR COMPONENT HAVING THROUGH-SILICON VIAS
    Publication number: 20210005515
    Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.
    Type: Application
    Filed: September 15, 2020
    Publication date: January 7, 2021
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • APPARATUSES, METHODS, AND SYSTEMS FOR A USER DEFINED FORMATTING INSTRUCTION TO CONFIGURE MULTICAST BENES NETWORK CIRCUITRY
    Publication number: 20200409701
    Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described.
    Type: Application
    Filed: June 29, 2019
    Publication date: December 31, 2020
    Inventors: Jian-Guo Chen, David T. Dougherty, Steven Pinault, Parakalan Venkataraghavan, Joseph Williams, Meng-Lin Yu, Kamran Azadet