Abstract: A resin composition is provided. The resin composition comprises an epoxy resin and a hardener, wherein the amount of the hardener is about 10 parts by weight to about 200 parts by weight per 100 parts by weight of the epoxy resin and the hardener comprises a first styrene-maleic anhydride copolymer (SMA) copolymer and a second SMA copolymer, the first SMA copolymer has a molar ratio of styrene to maleic anhydride m1, the second SMA copolymer has a molar ratio of styrene to maleic anhydride m2, and m1?m2?3.

Abstract: Disclosed is an epoxy resin composition for printed circuit board, which includes (A) an epoxy resin comprising a dicyclopentadiene type epoxy resin; (B) a copolymer of styrene and maleic anhydride as a curing agent; (C) a curing accelerator; (D) an optional silane dispersing agent; (E) an optional phosphorous-containing flame retardant; (F) an optional toughening agent; and (G) an optional inorganic filler.

Abstract: A battery car anti-theft device, which is mainly characterized in utilizing an electronic control circuit to control the external power supply state of a battery, and when set in the anti-theft state, if it is detected that the supply current is greater than a preset value, then the entire external power supply of the battery is immediately cut off, thus, there is no power supply to start the engine to enable the car thief to drive the vehicle away, thereby achieving the objective of preventing the vehicle from being stolen.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: Desirable composites of polysiloxane polymers and inorganic nanoparticles can be formed based on the appropriate selection of the surface properties of the particles and the chemical properties of the polymer. High loadings of particles can be achieved with good dispersion through the polymer. The composites can have good optical properties. In some embodiments, the inorganic particles are substantially free of surface modification.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: Installing computer software components on a client device for enabling connectivity to a host system by at least one of several different hardware devices typically includes receiving a connectivity component for enabling connectivity to a host system by at least one of several different hardware devices and detecting whether installation of the connectivity component is needed to enable connectivity between the client device and the host system. The connectivity component is typically installed on the client device when installation of the connectivity component is needed.

Abstract: A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A shortened process for producing a solution containing substantially purified capsular polysaccharides from a cellular Streptococcus pneumoniae lysate broth is described. Ultrafiltering and diafiltering a clarified S. pneumoniae lysate followed by pH adjustment to less than 4.5, preferably about 3.5, precipitated at least 98% of the protein in the solution without seriously affecting polysaccharide yield. Furthermore, following ultrafiltration and diafiltration and acidification to a pH of less than 4.5, filtration using activated carbon precipitated at least 90% of remaining protein without seriously affecting polysaccharide yield. Exemplary, non-limiting S. pneumoniae serotypes that can be purified using the shortened process of the invention are 1, 4, 5, 6A, 6B, 7F, 9V, 14, 18C, 19A, 19F, and 23F.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: An operation method of a wireless pointing input apparatus is provided. The operation method includes following steps. The displacement vector of the wireless pointing input apparatus is detected with a resolution. The displacement vector of the wireless pointing input apparatus is transmitted to a host in a wireless way every a time interval. The time interval is decreased correspondingly if the resolution is increased. Or, the time interval is increased correspondingly if the resolution is decreased.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.