Abstract: In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode.

Abstract: A multi-core processor supporting cache consistency, a method and apparatus for data writing, and a method and apparatus for memory allocation, as well as a system by use thereof. The multi-core processor supporting cache consistency includes a plurality of cores, the plurality of cores corresponding to respective local caches. A local cache of a core of the plurality of cores is responsible for caching data in a different range of addresses in a memory space and a core of the plurality of cores accesses data in a local cache of another core of the plurality of core via an interconnect bus.

Abstract: In one implementation, a power field-effect transistor (FET) having a reduced gate resistance includes a drain, a source, a gate, and a gate contact including a gate pad, a gate highway, and multiple gate buses. The gate buses are formed from a first metal layer having a first thickness, while the gate pad and the gate highway each include a metal stack including the first metal layer and a second metal layer. The second metal layer has a second thickness substantially greater than the first thickness, thereby reducing the gate resistance of the power FET.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a source region in a body region, a gate trench adjacent to the source region, and a source trench electrically coupled to the source region. The source trench includes a source trench conductive filler surrounded by a source trench dielectric liner, and extends into a drift region. The power semiconductor device includes a source trench implant below the source trench and a drain region below the drift region, where the source trench implant has a conductivity type opposite that of the drift region. The power semiconductor device may also include a termination trench adjacent to the source trench, where the termination trench includes a termination trench conductive filler surrounded by a termination trench dielectric liner. The power semiconductor device may also include a termination trench implant below the termination trench.

Abstract: The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Abstract: Detecting data dependencies of instructions associated with threads in a simultaneous multithreading (SMT) scheme is disclosed, including: dividing a plurality of comparators of an SMT-enabled device into groups of comparators corresponding to respective ones of threads associated with the SMT-enabled device; simultaneously distributing a first set of instructions associated with a first thread of the plurality of threads to a corresponding first group of comparators from the plurality of groups of comparators and distributing a second set of instructions associated with a second thread of the plurality of threads to a corresponding second group of comparators from the plurality of groups of comparators; and simultaneously performing data dependency detection on the first set of instructions associated with the first thread using the corresponding first group of comparators and performing data dependency detection on the second set of instructions associated with the second thread using the corresponding seco

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a trench having substantially parallel trench sidewalls, and a tapered dielectric liner in the trench. The tapered dielectric liner includes slanted dielectric sidewalls. A conductive filler is enclosed by the slanted dielectric sidewalls in the trench.

Abstract: A compound of Formula (I) is provided that has been shown to be useful for treating a disease, disorder or syndrome that is mediated by the inhibition of mycolic acid biosynthesis through inhibition of M. tuberculosis Enoyl Acyl Carrier Protein Reductase enzyme (InhA): wherein R1, R2, R3, R4 and R5 are as defined herein.

Abstract: A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.

Abstract: When a first transaction needs to conduct a writing operation to first data, after there is a determination that there exists a second transaction that has conducted a reading operation of the first data or is to conduct a reading operation of the first data, a record that indicates a conflict between the writing operation of the first transaction and the reading operation of the second transaction is generated. A processing of the second transaction is performed. After the processing is completed, the second transaction is submitted and the first transaction is notified according to the record. A processing of the first transaction is performed. After the processing is completed and a notification of the second transaction is received, the first transaction is submitted. The present techniques improve concurrently visiting transaction memory at a multi-core system, avoid rollbacks incurred by conflicts, and improve overall system performance.

Abstract: A method for sharing user information in browsers of a mobile terminal is disclosed in the present invention and comprises steps of: receiving a second operating command for importing the user information to a second browser; executing a first operating command for exporting the user information from the first browser in accordance with the second operating command for importing the user information to the second browser, and the first operating command is a command for exporting the user information from the first browser.

Abstract: Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: The present invention relates to a multi-branched Mannich base corrosion inhibitor and the method for preparing thereof. The method comprises (1) adding 3˜7 moles ketone and 3˜7 moles aldehyde to reaction kettle, adjusting pH to 2˜6 with acid, controlling temperature to 20˜50° C. and stirring for 20˜30 mins; (2) adding 1 mole organic polyamine to the reaction kettle under stirring, or adding the pH-adjusted ketone, aldehyde and organic solvent to organic polyamine, controlling temperature to 60˜90° C. and reacting for 1˜3 hrs, and after completion of the reaction, heating the system to 110° C. under nitrogen to remove water; the organic polyamine is organic compound comprising three or more primary amine groups and/or secondary amine groups.

Abstract: The present invention relates to a multi-touch display system that supports both multi-touch human input as well as input from a digital pen. The display system has a display panel that is configured to allow human touches along a front surface to be detected and tracked. The display panel also includes a location pattern that preferably covers the viewable areas of the display panel. The location pattern is configured to allow any location within the location pattern to be detected by analyzing a portion of the display pattern that is associated with the particular location. The digital pen is used to “write” on the display panel, wherein such a writing function involves detecting the location where writing occurs and controlling display content that is displayed on the display panel to reflect what is being written.

Abstract: A test strip detection system, comprising a test strip card (1) and a detection device (2); the test strip card (1) comprises a card box (16), a built-in test strip (15) and an electronic label (20) matched with the built-in test strip (15); the electronic label (20) stores parameters such as the standard working curve of an object to be detected and the like; the detection device (2) comprises an optical system (3), a photoelectric detector (4), an analog/digital converter (5), a data processing device (6), an electronic label read-write module (10) with an aerial (11), a voice module (34), a cell box (7) and an output display device (8). The system further comprises a wireless communication module (12) and a wireless network system (13) connected with the wireless communication module (12) and comprising a remote server (14).

Abstract: In one implementation, a trench field-effect transistor (trench FET) can include a semiconductor substrate including a drain region, a drift zone over the drain region, and first and second gate trenches including a gate dielectric and respective gate electrodes disposed therein, also over the drain region. The trench FET can further include a depletion trench situated between the first and second gate trenches, the depletion trench including a trench insulator. The trench insulator adjoins the gate electrodes and the gate dielectric so as to reduce a gate charge of the trench FET.

Abstract: In one implementation, a trench field-effect transistor (trench FET) includes a semiconductor substrate having a drain region, a drift zone over the drain region, and depletion trenches formed over the drain region. Each depletion trench includes a depletion trench dielectric and a depletion electrode. The trench FET can further include a respective bordering gate trench situated alongside each depletion trench, each bordering gate trench having a gate electrode and a gate dielectric. The gate dielectric is merged with the depletion trench dielectric between the depletion electrode and the gate electrode.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.