Abstract: A method for generating a preview associated with a media file is provided. The method may include receiving a plurality of social comments associated with a plurality of frames corresponding to the media file. The method may also include storing the received plurality of social comments in a repository, whereby the received plurality of social comments is stored with a frame marker. The method may further include analyzing the stored plurality of social comments. The method may additionally include classifying the analyzed plurality of social comments according to at least one sentiment and at least one keyword in the media file.

Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.

Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.

Abstract: Disclosed is a method for access authentication. The method includes: receiving profile information of a visitor through a server, and generating a visitor code and transmitting the same to a visitor terminal, and generating a random code based on a valid visitor code, and receiving a decoding result based on decoding the random code and the visitor code by the visit terminal, and predetermining an access authority for the visitor for a predetermined time as the decoding result is successfully matched.

Abstract: The invention relates to ester compounds of the general formula (I) to a process for preparation thereof and to the use thereof. These ester compounds may contain a mixture of at least two compounds of the general formula (I).

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based financial trading and applied to a distributed exchange set up based on a blockchain are provided. The distributed exchange includes a plurality of trading centers deployed in a distributed manner. One of the methods includes: receiving a trade order submitted by a user terminal in communication with a local trading center in the blockchain; transmitting the trade order to other trading centers in the blockchain and receiving trade orders from the other trading centers; generating an order book by performing an order matching process on the received trade orders, transmitting the generated order book to the other trading centers, and receiving order books from the other trading centers; and initiating a consensus process on the order books and executing the matched order in an order book for which consensus has been reached.

Abstract: A computer-implemented method for multi-thread processing, the method including: compiling a first plurality of threads using a corresponding first register set for each thread in the first plurality of threads, to obtain a first plurality of corresponding machine instruction codes; and fusing the first plurality of machine instruction codes using first instructions in an instruction set supported by a processing core, to obtain machine instruction code of a fused thread, the machine instruction code of the fused thread including thread portions corresponding to each thread of the first plurality of threads, in which the first instructions include load effective address instructions and control transfer instructions, in which the load effective address instructions and the control transfer instructions are compiled using a second register set, and in which jump operations between thread portions are implemented by the control transfer instructions inserted into the machine instruction code of the fused thread

Abstract: Methods and electronic circuits for executing instructions in a central processing unit (CPU) are provided. One of the methods includes forming an instruction block by sequentially fetching, from a current thread queue, one or more instructions including one jump instruction, wherein the jump instruction is the last instruction in the instruction block; transmitting the instruction block to a CPU execution unit for execution; replenishing the current thread queue with at least one instruction to form a thread queue to be executed; determining a target instruction of the jump instruction according to an execution result of the CPU execution unit; determining whether the target instruction is contained in the thread queue to be executed; and if not, flushing the thread queue to be executed, obtaining the target instruction and adding the target instruction to the thread queue to be executed.

Abstract: The present invention provides novel compositions and methods for assessing the size of tandem repeat sequences, e.g., telomeres, within a genome, using specially designed Molecular Inversion Probes (MIPs) and reaction conditions.

Abstract: An oil in water (o/w) micro-emulsion comprising: a. water; b. from about 3% up to about 30% oil; c. from about 0.1% up to about 10% lecithin; d. sucrose monoester as an emulsifier wherein the ratio of the combined amount of a lecithin and sucrose monoester to oil is less than 1; e. propylene glycol wherein the propylene glycol to water ratio by weight is greater than 1; and f. from about 14% up to about 40%, by weight, a sugar selected from the group consisting of fructose, glucose, and sucrose, and combinations thereof; wherein the mean droplet size of the o/w micro-emulsion is about 10 to about 80 nm.

Abstract: Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.

Abstract: A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.

Abstract: The invention relates to novel ester compounds of the general formula (I) to a process for preparation thereof and to the use thereof. These ester compounds may contain a mixture of at least two compounds of the general formula (I).

Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

Abstract: The present application relates to a semiconductor transistor device that includes a Schottky diode electrically connected in parallel to a body diode formed between a body region and a drift region. A diode junction of the Schottky diode is formed adjacent to the drift region and is arranged vertically above a lower end of the body region.

Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

Abstract: Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.

Abstract: Implementations of the present specification provide a method, an apparatus, and an electronic device for improving parallel performance of a CPU. The method includes: attempting to acquire data requests that are of a same type and that are allocated to the CPU core; determining a number of requests that are specified by the acquired one or more data requests; and in response to determining that the number of requests is greater than or equal to a maximum degree of parallelism: executing executable codes corresponding to the maximum degree of parallelism, wherein the maximum degree of parallelism is a maximum number of parallel threads executable by the CPU, and wherein the executable codes comprise code programs that are compiled and linked based on the maximum degree of parallelism at a time that is prior to a time of the executing.

Abstract: Provided are an immune cell capable of inducing the secretion of an anti-CD47 antibody when a CAR and/or an exogenous TCR is activated, a use thereof, and a preparation comprising the immune cell. Also provided are a preparation method of the immune cell and a kit for the preparation method.

Abstract: Implementations of this specification provide a method, an apparatus, and an electronic device for improving performance of a central processing unit (CPU) comprising a plurality of CPU dies. The method includes the following: enabling threads in each CPU die of the CPU to compete for a mutex of a respective CPU die; identifying the plurality of threads that have obtained the mutexes; enabling the plurality of threads that have obtained the mutexes to compete for a spin lock of the CPU; identifying, from the plurality of threads, a target thread that has obtained the spin lock; executing a critical section corresponding to the target thread that has obtained the spin lock; and releasing the mutex and the spin lock that are obtained by the target thread.