Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.

Abstract: The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

Abstract: Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.

Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

Abstract: A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen.

Abstract: A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first Static Random Access Memory (SRAM) cell.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.

Abstract: A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.

Abstract: The present disclosure relates to a device and method for fabricating a semiconductor memory device arrangement comprising a butted a contact arrangement configured to couple two transistors, wherein an active area of a first transistor is coupled to an active gate of a second transistor. The active gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active area of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.

Abstract: A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.

Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.

Abstract: A semiconductor structure includes a substrate, a conductive feature over the substrate, a conductive plug structure contacting a portion of an upper surface of the conductive feature, a first etch stop layer over another portion of the upper surface of the conductive feature, and a second etch stop layer over the first etch stop layer. The first etch stop layer is a doped etch stop layer. The first etch stop layer is to function as an etch stop layer during a predetermined etching process for etching the second etch stop layer.

Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.

Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.

Abstract: A rapid thermal anneal system and method for processing a semiconductor substrate. The system includes a chamber configured for holding a semiconductor substrate, a heating lamp array, and a process controller operably connected to the lamp array for controlling a heating cycle of the substrate. The lamp array includes a plurality of lamps positioned to heat the substrate. The controller is operable to energize or de-energize each lamp on an individual basis, and further to simultaneously energize one or more localized groups or clusters of lamps each having at least two adjacent lamps arranged for heating geographically localized regions of the substrate having special heating needs. The system is further operable to energize all lamps in the array simultaneously. The system and method provides the capability to perform customized substrate annealing.

Abstract: A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.

Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

Abstract: The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.

Abstract: The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.