Patents by Inventor Ling-Sung Wang
Ling-Sung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130207166Abstract: A semiconductor device system, structure and method of manufacture of a source/drain with SiGe stressor material to address effects due to dopant out-diffusion are disclosed. In an embodiment, a semiconductor substrate is provided with a gate structure, and recesses for source and drain are formed on opposing sides of the gate structure. Doped stressors are embedded into the recessed source and drain regions, and a plurality of layers of undoped stressor, lightly doped stressor, highly doped stressor, and a cap layer are formed in an in-situ epitaxial process. In another embodiment the doped stressor material is boron doped epitaxial SiGe. In an alternative embodiment an additional layer of undoped stressor material is formed.Type: ApplicationFiled: February 10, 2012Publication date: August 15, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20130200442Abstract: A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan LIN, Chih-Hsun LIN, Ching-Hua CHU, Ling-Sung WANG
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Patent number: 8476629Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.Type: GrantFiled: September 27, 2011Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Patent number: 8470660Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.Type: GrantFiled: September 16, 2011Date of Patent: June 25, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mei-Hsuan Lin, Chih-Kang Chao, Chih-Hsun Lin, Ling-Sung Wang
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Publication number: 20130157467Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jen-Yi CHEN, Kun-Ei CHEN, Ling-Sung WANG, Chen-Chieh CHANG
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Patent number: 8468474Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.Type: GrantFiled: September 14, 2012Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Publication number: 20130111419Abstract: The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan Lin, Ling-Sung Wang, Chih-Hsun Lin, Chih-Kang Chao
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Publication number: 20130093047Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20130087857Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. In an example, the method includes providing a substrate; forming a gate structure over the substrate; removing portions of the substrate to form a first recess and a second recess in the substrate, such that the gate structure interposes the first recess and the second recess; forming a nitrogen passivation layer in the substrate, such that the first recess and the second recess are defined by nitrogen passivated surfaces of the substrate; and forming doped source and drain features over the nitrogen passivated surfaces of the first recess and the second recess, the doped source and drain features filling the first and second recesses.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Yang Ko, Ching-Chien Huang, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20130087885Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Ling-Sung Wang, Chi-Yen Lin
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Publication number: 20130075725Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.Type: ApplicationFiled: September 27, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Publication number: 20130071995Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan Lin, Chih-Kang Chao, Chih-Hsun Lin, Ling-Sung Wang
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Publication number: 20130069162Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.Type: ApplicationFiled: September 15, 2011Publication date: March 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan Lin, Chih-Chan Lu, Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang, Jen-Pan Wang
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Publication number: 20130049781Abstract: Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia Yang Ko, Ying-Han Chiou, Ling-Sung Wang
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Publication number: 20130043590Abstract: The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan LIN, Chih-Hsun LIN, Chih-Kang CHAO, Ling-Sung WANG
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Publication number: 20130024833Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Publication number: 20130020717Abstract: An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Hsuan LIN, Chih-Hsun LIN, Chih-Kang CHAO, Ling-Sung WANG
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Publication number: 20130002263Abstract: A method of reliability testing of a semiconductor device is described. The embodiment, includes providing a capacitor including an insulating layer interposing two conductive layers. A plurality of voltages are provided to the capacitor including providing a first voltage and a second voltage greater than the first voltage. A leakage associated with the capacitor is measured while applying the second voltage. In an embodiment, the leakage measured while applying the second voltage indicates that a failure of the insulating layer of the capacitor has occurred. In an embodiment, the capacitor is an inter-digitated metal-oxide-metal (MOM) capacitor. The reliability testing may be correlated to TDDB test results. The reliability testing may be performed at a wafer-level.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Huang Jiun-Jie, Chi-Yen Lin, Ling-Sung Wang, Chih-Fu Chang
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Patent number: 8341562Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.Type: GrantFiled: July 21, 2011Date of Patent: December 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Publication number: 20120313186Abstract: A polysilicon gate structure includes a substrate, a silicon dioxide layer disposed over the substrate, a nitrogen-doped high-k dielectric layer disposed over the silicon dioxide layer, and a polysilicon gate disposed over the nitrogen-doped high-k dielectric layer.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Chien HUANG, Ying-Han CHIOU, Ling-Sung WANG