Abstract: A new method is provided for the creation of a hole through a layer of insulating material. The method provides for combining a feed-forward method with a feed backward method and a high-polymer based hole profile, in order to establish a hole of a constant Critical Dimension for the hole bottom, making the CD of the hole bottom independent of the CD of the opening created through the overlying developed layer of photoresist and independent of the thickness of the layer of insulator material after CMP has been applied to the surface of the insulation layer.

Abstract: Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.

Abstract: Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.

Abstract: Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidation, such that the trench is sealed and a space is formed within the layer of silicon oxide. The space can contain a vacuum or any of a variety of gases depending upon conditions of the thermal oxidation step. Retrograde trench isolation structures containing a space are also provided.

Abstract: A new process is provided for the creation of an ESD protection circuit. The invention starts with a first conventional gate electrode and a second gate electrode that is designated as being the gate electrode that provides the ESD protection function. The contact surfaces of the first and second gate electrode are salicided, an etch stop layer is deposited which serves as an etch stop for the creation of contact openings to the contact surfaces of the second gate electrodes. The etch stop layer is removed from the surface of the source/drain regions of the second (that is the ESD) gate electrode. A layer of dielectric is deposited over the first and the second gate electrodes, contact openings are created through the layer of dielectric to the source/drain contact surfaces of the first and second gate electrodes. Significantly, an overetch into the source/drain regions of the second (the ESD) gate electrode occurs during this contact etch. The contact openings are filled with a metal.

Abstract: A self aligned MIM capacitor structure and method for forming the same, the method including forming a metal filled damascene having an exposed surface in a dielectric insulating layer; forming a metal precursor layer on the exposed surface; carrying out a process on the metal precursor layer selected from the group consisting of oxidation and nitridation to form a capacitor dielectric portion; and, forming a conductive electrode on the capacitor dielectric portion.

Abstract: Methods are provided for making retrograde trench isolation structures with improved electrical insulation properties. One method comprises the steps of: forming a retrograde trench in a silicon substrate, and forming a layer of silicon oxide on the walls of the trench by thermal oxidation, such that the trench is sealed and a space is formed within the layer of silicon oxide. The space can contain a vacuum or any of a variety of gases depending upon conditions of the thermal oxidation step. Retrograde trench isolation structures containing a space are also provided.

Abstract: A method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode is deposited over the layer of gate oxide. The gate electrode is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Abstract: A new method is provided for the creation of a hole through a layer of insulating material. The method provides for combining a feed-forward method with a feed backward method and a high-polymer based hole profile, in order to establish a hole of a constant Critical Dimension for the hole bottom, making the CD of the hole bottom independent of the CD of the opening created through the overlying developed layer of photoresist and independent of the thickness of the layer of insulator material after CMP has been applied to the surface of the insulation layer.

Abstract: A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Abstract: A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Abstract: A new layer of RPO is provided for semiconductor devices, specifically for semiconductor device having sub-micron device feature size. The layer of RPO that is provided by the invention comprises a layer of silicon-rich CVD oxide, having a refractive index of between about 1.57 and 1.60 to prevent silicon atoms that are present in a layer of polysilicon from diffusing into the overlying layer of resist protect oxide.

Abstract: A self-aligned fabricating process and a structure of ETOX flash memory. A plurality of parallel lines for device isolation is formed in a substrate, and then forming a plurality of parallel stacked gates above the substrate. The device isolation lines and the stacked gates are perpendicular to each other. A plurality of first insulation layers is formed such that an insulation layer is formed over each stacked gate. Spacers are also formed over the sidewalls of each stacked gate. A plurality of source arrays and drain arrays are formed in the substrate between neighboring stacked gates. The source and drain arrays are parallel to the stacked gates, with a source array and a drain array formed in alternating positions between the stacked gates. Each source array comprises a plurality of source-doped regions located between the device isolation lines respectively. Similarly, each drain array has a plurality of drain-doped regions located between the device isolation lines.

Abstract: A method of fabricating a dual-oxide STI comprising the following steps. A structure having an STI opening formed therein is provided. An HDP silicon oxide layer portion is formed within the STI opening, partially filling the STI opening. A planarized HDP silicon-rich-oxide cap layer is formed upon the HDP silicon oxide layer portion, filling the STI opening to form the dual-oxide STI, whereby any unlanded contact window formed through an overlying interlevel dielectric layer exposing a portion of the dual-oxide STI only exposes a portion of the HDP silicon-rich-oxide cap layer.

Abstract: A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, wherein the underlying component of the composite insulator spacer is comprised of a thin silicon oxide layer obtained via chemical vapor deposition procedures using tetraethylorthosilicate (TEOS), as a source, has been developed. To densify the underlying thin silicon oxide layer an anneal procedure usually performed after implantation of ions used for a lightly doped source/drain region, is delayed and performed after deposition of the thin silicon oxide layer. The anneal procedure is then used for both activation of the lightly doped source/drain ions, and densification of the thin silicon oxide layer. The etch rate of the densified silicon oxide layer, in dilute hydrofluoric acid procedures is now reduced allowing the underlying silicon oxide component, of the composite insulator spacer, to survive subsequent wet clean procedures employing dilute hydrofluoric acid.

Abstract: A method of forming a self-aligned mask ROM. Gate stacks that serve as word lines are formed over a substrate. Each gate stack includes a gate oxide layer, a gate conductive layer and a gate cap layer. Spacers are next formed on the sidewalls of the gate stacks. An insulation layer is deposited over the substrate and the gate stacks. The insulation layer is planarized to expose the gate cap layer. A patterned photoresist layer is formed over the insulation layer to expose the ion implant regions needed for programming. Using the patterned photoresist layer as an etching mask, the gate cap layer within each ion implant region is removed to expose the gate conductive layer using an etchant with high etching selectivity. Using the patterned photoresist layer as an implant mask, ions are implanted into the substrate via the ion implant regions so that the mask ROM is programmed. Finally, the photoresist layer is removed.

Abstract: A method of forming a desired rectangular pattern in a material layer above a substrate. The method includes providing a substrate having a material layer thereon. A hard mask layer is next formed over the material layer, and then a first photoresist layer having a first pattern therein is formed over the hard mask layer. A first etching operation is carried out while using the first photoresist layer as an etching mask to remove a portion of the hard mask layer, thereby transferring the pattern in the first photoresist layer to the hard mask layer. The first photoresist layer is removed. A second photoresist layer having a second pattern therein is formed over the substrate. A second etching operation is carried out to remove a portion of the material layer while using the patterned second photoresist layer and the hard mask layer as an etching mask. Hence, the desired rectangular pattern is formed in the material layer.

Abstract: A process for manufacturing flash memories is disclosed. In one embodiment, a first oxide layer is deposited over a substrate and then, a first polysilicon layer is deposited over the oxide layer. When the first polysilicon layer is etched and formed, an ONO (oxide nitride oxide) layer is deposited over the first polysilicon layer. Then, portions of the ONO layer and the first polysilicon layer are removed to form two nitride fences. A tunnel oxide layer in a conformal shape is subsequently deposited over said nitride fences, some portions of the first oxide layer, and said substrate. After depositing of tunnel oxide layer, a floating gate polysilicon layer, a second oxide layer, and a second polysilicon layer are deposited. Portions of the second polysilicon layer, the second oxide layer, the floating gate layer, and the tunnel oxide layer are, subsequently, removed. Finally, a drain well and a source well are formed in the substrate.

Abstract: A fabrication method of a device isolation structure. A patterned mask layer is formed on a silicon substrate. A dopant is doped into an exposed substrate to prevent a bird's beak silicon region from being oxidized in a first doping step. A spacer is formed on the sidewall of the mask layer. Portions of the silicon substrate are removed to form a trench by using the mask layer and the spacer as a mask. A second dopant is doped into the exposed silicon substrate on the bottom of the trench to benefit the oxidation of a desired field oxide region in a second doping step. A field oxide layer is formed to fill the trench in a field oxide process.

Abstract: The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region.