Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: An apparatus for determining cardiac performance in the patient. The apparatus includes a conductance catheter for measuring conductance and blood volume in a heart chamber of the patient. The apparatus includes a processor for determining instantaneous volume of the ventricle by applying a non-linear relationship between the measured conductance and the volume of blood in the heart chamber to identify mechanical strength of the chamber. The processor is in communication with the conductance catheter. Methods for determining cardiac performance in a patient. Apparatuses for determining cardiac performance in a patient.

Abstract: A signal generating apparatus includes: a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: An apparatus for determining cardiac performance in the patient involving a conductance catheter (12) for measuring conductance and blood volume in a heart chamber of the patient. The apparatus includes a processor (14) for determining instantaneous volume of the ventricle by applying a non-linear relationship between the measured conductance and the volume of blood in the heart chamber to identify mechanical strength of the chamber. The processor (14) is in communication with the conductance catheter (12).

Abstract: A method for browsing photo files in an embedded electronic device includes the following steps. A user interface window is displayed on a display. The user interface window includes a navigator bar and a content display area for showing photos, and at least one control button is loaded on the navigator bar for executing control functions to the photos. The electronic device detects if an external storage device is connected to the electronic device. A new resource button linking to the external storage device is created on the navigator bar when the external storage device is connected. Thumbnail image of each photo file from the external storage device is displayed on the content display area.

Abstract: A file sharing system includes a web server, a first electronic device, and a second electronic device. The web server includes an authorizing module and a server storage module. The server storage module is capable of storing files uploaded from a first electronic device. The authorizing module is capable of recording an authorizing setting from the first electronic device to authorize a second electronic device to access the files in the server storage module.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: A temperature compensated oscillation circuit capable of providing a stable frequency output over temperature is provided, in which an oscillator with a crystal resonator is arranged to generate an oscillation signal with an output frequency, and a temperature sensor provides a temperature compensation voltage of which a function is linear with respect to an ambient temperature of the oscillator. A first accumulation mode MOS varactor is coupled to the oscillator, and the first accumulation mode MOS varactor adjusts a capacitance thereof in response to the temperature compensation voltage, such that the coupled oscillator has a frequency compensation over temperature for the oscillation signal, wherein the frequency compensation substantially varies as an inverse function of a deviation of the crystal resonator over temperature when the ambient temperature is within a predetermined temperature range.

Abstract: A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator.

Abstract: A phase locked loop (PLL) directly uses a charge pump and loop filter therein for fast and low-costly calibration. The PLL comprises a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to adjust the time measured by the counting device to a desired time.

Abstract: The present invention provides a method of fast image construction. The wavelength information is extracted in advance based on characteristics of a Fourier domain Optical Coherent Tomography (OCT) system, to obtain a vector of wavelengths which are in a uniform distribution in a wave number space, and thus to obtain a virtual position coefficient of this wavelength vector at a CCD, from which a weight matrix is calculated based on a transfer function for a discrete Fourier transform with zero-padding interpolation. In operation of the system, the interpolation is carried out based on the weight matrix and collected data, or is carried out based on the weight matrix which has been truncated by being subject to windowing and the collected data, to obtain interpolated data satisfying requirements.

Abstract: A KVM switch device is provided. The KVM switch device comprises a frame, a switch part fixed to the frame, a console unit movably connected to the switch part, and a sliding mechanism disposed between the console unit and the frame, wherein the switch part communicates with the console unit. The sliding mechanism comprises at least one guide rod disposed on the frame and at least one sliding bearing sliding along the guide rod. The console unit is movable between a closed position and an open position by the sliding bearing sliding along the guide rod.

Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Abstract: The present invention relates to tetraaza phenalen-3-one compounds which inhibit poly (ADP-ribose) polymerase (PARP) and are useful in the chemosensitization of cancer therapeutics. The induction of peripheral neuropathy is a common side-effect of many of the conventional and newer chemotherapies. The present invention further provides means to reliably prevent or cure chemotherapy-induced neuropathy. The invention also relates to the use of the disclosed PARP inhibitor compounds in enhancing the efficacy of chemotherapeutic agents such as temozolomide. The invention also relates to the use of the disclosed PARP inhibitor compounds to radiosensitize tumor cells to ionizing radiation. The invention also relates to the use of the disclosed PARP inhibitor compounds for treatment of cancers with DNA repair defects.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a phase-locked loop device for generating a synthesized signal, wherein the phase-locked loop device includes a phase detector, a charge pump device, a filtering device, a controllable oscillator, and a switch device coupled to the controllable oscillator for selectively coupling the controllable oscillator to the filtering device or a tuning reference signal; a calibration controller generates a tuning reference signal and controls the switch device; and a first calibrator tunes the controllable oscillator into a predetermined sub-band according to a reference oscillating signal and a synthesized signal when the switch device couples the controllable oscillator to the tuning reference signal of the calibration controller.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.

Abstract: A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine.