Patents by Inventor Ling Yi

Ling Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11568429
    Abstract: A demand forecasting method and a demand forecasting apparatus are provided. A preliminary prediction amount corresponding to a part number is obtained based on historical demand data. A demand probability of the part number is calculated based on the preliminary prediction amount. A prediction demand amount corresponding to the part number is obtained based on the historical demand data, the preliminary prediction amount and the demand probability.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 31, 2023
    Assignee: Wistron Corporation
    Inventors: Chi Lin Tsai, Chi Hao Yu, Wen Hsuan Lan, Ling-Yu Kuo, Han-Yi Shih, Pei Yu Ho
  • Patent number: 11566422
    Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: January 31, 2023
    Assignee: MINIWIZ CO., LTD.
    Inventors: Chian-Chi Huang, Tzu-Wei Liu, Jui-Ping Chen, Yu-Ying Yai, Yu-Tung Hsing, Pei-Yi Huang, Min-Wei Lin, Yi-Chun Chang, Ling-Hsiang Weng
  • Patent number: 11563102
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Carlos H. Diaz, Chih-Sheng Chang, Cheng-Yi Peng, Ling-Yen Yeh
  • Publication number: 20230017846
    Abstract: Embodiments disclose a package structure and a fabricating method. The package structure includes: a semiconductor chip; a first non-conductive layer covering a front surface of the semiconductor chip and part of a side wall of the semiconductor chip; a second non-conductive layer positioned on an upper surface of the first non-conductive layer and covering at least part of a side wall of the first non-conductive layer, wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; a substrate; and a solder mask layer positioned on a surface of the substrate, where a first opening is provided in the solder mask layer. The semiconductor chip is flip-chip bonded on the substrate, a surface of the second non-conductive layer away from the first non-conductive layer and a surface of the solder mask layer away from the substrate are bonding surfaces.
    Type: Application
    Filed: September 26, 2022
    Publication date: January 19, 2023
    Inventor: LING-YI CHUANG
  • Publication number: 20230007857
    Abstract: Embodiments provide enhanced performance diagnosis in a network computing environment. In response to an occurrence of a performance issue for a node while under operating conditions, common logs for applications on the node are analyzed. The applications are respectively registered in advance for diagnosis services. The applications each register rules in advance for the diagnosis services. At a time of the performance issue, debug programs are automatically issued to generate debug level logs respectively for the applications. Debug level logs are analyzed according to the rules to determine a root cause of the performance issue. A potential solution to the root cause of the performance issue is determined using the rules, without having to recreate the operating conditions occurring during the performance issue. The potential solution to rectify the root cause of the performance issue is executed without having to recreate the operating conditions occurring during the performance issue.
    Type: Application
    Filed: July 7, 2021
    Publication date: January 12, 2023
    Inventors: Jie Yang, Yao Zhao, Fei Tan, Xin Yu Pan, Ling Qin, Pin Yi Liu, Wei Wu, Jiang Yi Liu
  • Publication number: 20230009114
    Abstract: A method for forming a semiconductor structure is provided. The method includes: providing a substrate; forming a groove in the substrate, in which a side wall of the groove is formed by sequential connection of a plurality of pits recessed into the substrate; forming a first material in the groove, in which the pits are completely filled with the first material; and exposing and developing the first material in the groove to obtain a through via structure.
    Type: Application
    Filed: February 10, 2022
    Publication date: January 12, 2023
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230011266
    Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided, and the substrate includes an active surface and a back surface opposite to the active surface. An etching stop layer is formed on the back surface of the substrate. The substrate is fixed onto a first temporary carrier to make the etching stop layer be located between the substrate and the first temporary carrier. The substrate is etched until reaching the etching stop layer to form a via structure penetrating through the substrate.
    Type: Application
    Filed: February 17, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230010585
    Abstract: Provided is a packaging method, including: providing a base with a groove in its surface, which includes at least one pad exposed by the groove; providing a chip having a first surface and a second surface opposite to each other, at least one conductive bump being provided on the first surface of the chip; filling a first binder in the groove; applying a second binder on the first surface of the chip and the conductive bump; and installing the chip on the base, the conductive bump passing through the first binder and the second binder to connect with the pad.
    Type: Application
    Filed: February 10, 2022
    Publication date: January 12, 2023
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230005868
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, and a first bonding structure and a first conductive via which are formed in the first substrate. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than a melting point of the first metal layer. The first metal layer includes a first surface and a second surface arranged opposite to each other. The first surface of the first metal layer is provided with a first groove, and the second metal layer is arranged in the first groove. The first conductive via is in contact with the second surface of the first metal layer. A projection of the first conductive via coincides with a projection of the first groove in a direction perpendicular to the first surface of the first metal layer.
    Type: Application
    Filed: February 10, 2022
    Publication date: January 5, 2023
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230005849
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor group and a second conductor group, and the second conductive contact pad includes a third conductor group and a fourth conductor group.
    Type: Application
    Filed: January 19, 2022
    Publication date: January 5, 2023
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230005867
    Abstract: A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.
    Type: Application
    Filed: February 11, 2022
    Publication date: January 5, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi CHUANG
  • Publication number: 20230005866
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip, where a first conductive connection wire of the first chip is connected to a first conductive contact pad, a second conductive connection wire of the second chip is connected to a second conductive contact pad, the first conductive contact pad includes a first conductor group and a first connection group, and the second conductive contact pad includes a second conductor group and a second connection group.
    Type: Application
    Filed: January 19, 2022
    Publication date: January 5, 2023
    Inventor: Ling-Yi CHUANG
  • Patent number: 11545468
    Abstract: A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer, wherein an upper surface of the first wafer includes a first bonding pad configured to connect to a first signal; fabricating a first redistribution layer (RDL) on the first wafer, comprising a first wiring electrically connected to the first bonding pad, and the first wiring includes a first landing pad; bonding a second wafer on the first RDL, wherein the second wafer includes a second bonding pad configured to connect the first signal and located corresponding to the first bonding pad; fabricating a first through silicon via (TSV) with a bottom connected to the first landing pad at a position corresponding to the first landing pad; and fabricating a second RDL on the second wafer to connect the second bonding pad and the first TSV. This wafer stacking method improves the manufacturing yield.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: January 3, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Ling-Yi Chuang, Shu-Liang Ning
  • Publication number: 20220415784
    Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a first wafer and a second wafer. A surface of the first wafer has a first electrode plate, a first dielectric layer and a first dummy pad stacked in sequence to constitute a capacitor; and the surface of the first wafer further has a first functional pad, and the first functional pad and the first dummy pad are arranged on a same layer. The second wafer is bonded to the first wafer, and a surface of the second wafer has a second dummy pad and a second functional pad arranged on a same layer. The first dummy pad is bonded to the second dummy pad, and the first functional pad is bonded to the second functional pad.
    Type: Application
    Filed: September 6, 2022
    Publication date: December 29, 2022
    Inventor: LING-YI CHUANG
  • Publication number: 20220390920
    Abstract: A method for constructing a body-in-white (BiW) spot welding deformation prediction model based on a graph convolutional network (GCN) includes: 1) acquiring a welding feature and 3D coordinates of a spot weld to form an eigenvector and extracting designed 3D coordinates at each 3D coordinate measurement point; 2) encoding, by an encoder, eigenvectors and designed 3D coordinate vectors into hidden space vectors of spot welds and hidden space vectors of the coordinate measurement points, respectively, and constructing a graph topology G through a k-nearest neighbors algorithm; 3) decomposing a Laplacian eigenvector of the constructed graph topology G to acquire frequency domain components, and linearly transforming eigenvalues corresponding to the frequency domain components to construct a multi-layer GCN; 4) inputting the thermodynamic and kinetic information of each coordinate measurement point into a deep neural network and decoding a final deformation at each coordinate measurement point; and 5) optimizing
    Type: Application
    Filed: June 2, 2022
    Publication date: December 8, 2022
    Applicant: Chongqing University
    Inventors: Shilong WANG, Bo YANG, Lili YI, Ling KANG, Yu WANG
  • Patent number: 11488917
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor and a second conductor, and the second conductive contact pad includes a third conductor and a fourth conductor. The first conductor is directly opposite to the fourth conductor, and the second conductor is directly opposite to the third conductor. Therefore, pre-connection of the first conductive contact pad and the second conductive contact pad may be implemented and then the first chip and second chip that are pre-connected are transferred for bonding.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: November 1, 2022
    Assignee: GHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ling-Yi Chuang
  • Patent number: 11480531
    Abstract: An assessment system includes a storage device and a processing circuit. The processing circuit is coupled to the storage device and configured to execute the instructions stored in the storage device. The storage device is configured for storing instructions of extracting at least one feature parameter corresponding to at least one defect detected on an object respectively; determining at least one feature evaluation according to the at least one feature parameter respectively; weighting the at least one feature evaluation to calculate at least one weighted feature evaluation respectively; summing the at least one weighted feature evaluation to calculate at least one total score corresponding to at least one lesson-learnt case; and ranking the at least one total score corresponding to the at least one lesson-learnt case to find out a suspected root cause corresponding to one of the at least one lesson-learnt case with higher priority.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: October 25, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ge Ge Zhao, Fei Wang, Zheng Yi Cai, Ling Ling Fu, Tao Huang, Xing Jin, Jing Yun Wu, Yadong Wang
  • Patent number: 11463350
    Abstract: In one embodiment, a method comprises: determining, by a network device that is configured for joining a local directed acyclic graph (DAG) instance in a data network, an unreachability by the network device to any member of the local DAG instance; generating and broadcasting, by the network device, a request message that identifies the network device requesting to join the local DAG instance, the request message causing a neighboring network device in a global DAG instance of the data network to rebroadcast the request message for reception by a member of the local DAG instance, the neighboring network device a non-member of the local DAG instance; and receiving, by the network device, a reply message indicating a member of the local DAG instance is reachable via the neighboring network device in the global DAG instance.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: October 4, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Ling Wei, Wenjia Wu, Nan Yi, Chuanwei Li
  • Publication number: 20220251831
    Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 11, 2022
    Applicant: MINIWIZ CO.,LTD.
    Inventors: Chian-Chi HUANG, Tzu-Wei LIU, Jui-Ping CHEN, Yu-Ying YAI, Yu-Tung HSING, Pei-Yi HUANG, Min-Wei LIN, Yi-Chun CHANG, Ling-Hsiang WENG
  • Publication number: 20220238523
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE