Abstract: According to various embodiments, a viewing event may be detected, the viewing event corresponding to a user viewing a content item. A view reason associated with the viewing event may be determined, the view reason indicating how the user was notified of the content item or how the user accessed the content item. A privacy value associated with the viewing event may be determined, the privacy value indicating an inferred sensitivity of the user to publication of the viewing event. Further, metadata describing the viewing event may be generated. Moreover, the metadata may be associated with the content item.

Abstract: A computer-implemented method is provided for a management entity to detect where a rogue access point is connected to the network infrastructure. The management entity receives from a wireless network controller an indication of an unauthorized frame wirelessly intercepted by an authorized access point. The unauthorized frame carries data between a rogue access point and a wireless client device. The rogue access point is connected to a compromised network element in a managed network at a compromised port of the compromised network element. The management entity extracts a client network address and a gateway network address from the indication of the unauthorized frame. The management entity traces a path through the managed network from a gateway network element associated with the gateway network address to the compromised network element. The management entity determines the compromised port in the compromised network element at which the rogue access point is connected.

Abstract: According to various embodiments, a viewing event may be detected, the viewing event corresponding to a user viewing a content item. A view reason associated with the viewing event may be determined, the view reason indicating how the user was notified of the content item or how the user accessed the content item. A privacy value associated with the viewing event may be determined, the privacy value indicating an inferred sensitivity of the user to publication of the viewing event. Further, metadata describing the viewing event may be generated. Moreover, the metadata may be associated with the content item.

Abstract: A semiconductor chip includes a substrate and a semiconductor layer positioned above the substrate. A hybrid through-silicon via (“TSV”) extends continuously through at least the semiconductor layer and the substrate and includes a first TSV portion and a second TSV portion. A lower portion of the first TSV portion is positioned in the substrate and has a lower surface adjacent to a back side of the substrate and an upper surface below the semiconductor layer. Upper sidewall portions of the first TSV portion extend from the upper surface through at least the semiconductor layer. A depth of the lower portion is greater than a thickness of the upper sidewall portions. The second TSV portion is conductively coupled to the first TSV portion, is laterally surrounded by the upper sidewall portions, and extends continuously from the upper surface through at least the semiconductor layer.

Abstract: According to various embodiments, a viewing event may be detected, the viewing event corresponding to a user viewing a content item. A view reason associated with the viewing event may be determined, the view reason indicating how the user was notified of the content item or how the user accessed the content item. A privacy value associated with the viewing event may be determined, the privacy value indicating an inferred sensitivity of the user to publication of the viewing event. Further, metadata describing the viewing event may be generated. Moreover, the metadata may be associated with the content item.

Abstract: A semiconductor chip includes a substrate and a semiconductor layer positioned above the substrate. A hybrid through-silicon via (“TSV”) extends continuously through at least the semiconductor layer and the substrate and includes a first TSV portion and a second TSV portion. A bottom plug portion of the first TSV portion is positioned in the substrate and has a lower surface adjacent to a back side of the substrate and an upper surface below the semiconductor layer. Upper sidewall portions of the first TSV portion extend from the upper surface through at least the semiconductor layer. A depth of the bottom plug portion is greater than a thickness of the upper sidewall portions. The second TSV portion is conductively coupled to the first TSV portion, is laterally surrounded by the upper sidewall portions, and extends continuously from the upper surface through at least the semiconductor layer.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.

Abstract: Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.

Abstract: According to various embodiments, a viewing event may be detected, the viewing event corresponding to a user viewing a content item. A view reason associated with the viewing event may be determined, the view reason indicating how the user was notified of the content item or how the user accessed the content item. A privacy value associated with the viewing event may be determined, the privacy value indicating an inferred sensitivity of the user to publication of the viewing event. Further, metadata describing the viewing event may be generated. Moreover, the metadata may be associated with the content item.

Abstract: Techniques for facilitating the promotion of content are described. Consistent with some embodiments, a content promotion interface is presented with a content item, enabling a user to promote the content item. By promoting the content item, the user can influence one or more algorithms used in selecting and presenting content items to other users, such that the promoted content item is provided preferential processing and may be selected for presentation in situations where it may otherwise not be (e.g., if not promoted), and the promoted content item may be presented in a manner designed to garner more collective user-attention than the content item would otherwise receive, if presented in a conventional manner (e.g., without having been promoted).

Abstract: Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.

Abstract: A credit mechanism or system for use with a network-based application is described. The credit mechanism operates in conjunction with the network-based application to require that users pay a number of credits to interact with other users. The number of credits required to interact with a particular user may be determined using an algorithm that takes as input a number of signals that are inferred from observed data and which generally represent a measure of the particular user's willingness to provide time and attention (e.g., supply of attention), and a measure of the desire of other users to obtain the particular user's attention (e.g., demand for attention).

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process.

Abstract: Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion.

Abstract: A dual damascene structure comprising a composite barrier/etch stop layer including a lower silicon carbide (SiC) layer and an upper first oxygen doped SiC layer formed over a substrate is provided. A first dielectric layer is formed over the first oxygen doped SiC layer followed by a second oxygen doped SiC etch stop layer, and a second dielectric layer. An opening with a via and an overlying trench extends through the second dielectric layer, the second oxygen doped SiC etch stop layer, the first dielectric layer, the upper first oxygen doped SiC layer and at least a portion of the lower silicon carbide (SiC) layer. The opening is filled with a diffusion barrier layer and a metal layer.

Abstract: An example embodiment of a method of forming a semiconductor device comprising the following. We form at least a first transistor over a first region of a substrate and forming at least a second transistor over a second region of the substrate. We form a stress layer over the first and second transistors. We form an electromagnetic radiation blocking layer over the second transistor and not over the first transistor. In an exposure step, we expose the electromagnetic radiation blocking layer over the second transistor and exposing the stress layer over the first transistor to electromagnetic radiation to form a cured stress layer over the first transistor. The cured stress layer has a different stress than the stress layer. We may remove the electromagnetic radiation blocking layer.

Abstract: A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overlies a conductive interconnect structure that couples to semiconductor devices that are susceptible to plasma-induced damage during high density plasma deposition processes. A silicon-rich oxide is deposited in-situ immediately following the deposition of the USG liner so as to form a silicon-rich oxide liner that directly overlies the USG liner. The silicon-rich oxide liner protects the interconnect structure during the subsequent high density plasma deposition process, preventing damage resulting from plasma charge to the interconnect structure.

Abstract: A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.

Abstract: A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600° C. is provided. From about 10 to 200 sccm PH3 gas, from about 50 to 4000 sccm N2 gas and from about 50 to 1000 sccm NH3 gas are introduced into the CVD reaction chamber. Either from about 10 to 200 sccm O2 gas or from about 50 to 1000 sccm N2O gas is introduced into the CVD reaction chamber. An HFRF power of from about 0 watts to 4 kilowatts is also employed. An LFRF power of from about 0 to 5000 watts may also be employed. Employing a phoslon etch stop layer in a borderless contact fabrication. Employing a phoslon lower etch stop layer and/or a phoslon middle etch stop layer in a dual damascene fabrication.