Patents by Inventor Lixin Zhang

Lixin Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8745618
    Abstract: A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jiang Lin, Lixin Zhang
  • Patent number: 8739159
    Abstract: A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jiang Lin, Lixin Zhang
  • Publication number: 20140080208
    Abstract: Provided are adenoviral vectors for generating an immune response to antigen. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal sequence upstream of a tumor antigen upstream of CD40 ligand, which is missing all or substantially all of the transmembrane domain rendering CD40L secretable. Also provided are methods of generating an immune response against cells expressing a tumor antigen by administering an effective amount of the invention vector. Further provided are methods of generating an immune response against cancer expressing a tumor antigen in an individual by administering an effective amount of the invention vector. Still further provided are methods of generating immunity to infection by human papilloma virus (HPV) by administering an effective amount of the invention vector which encodes the E6 or E7 protein of HPV. The immunity generated is long term.
    Type: Application
    Filed: August 23, 2013
    Publication date: March 20, 2014
    Applicant: VAXum, LLC
    Inventors: Albert B. Deisseroth, Lixin Zhang
  • Publication number: 20140072663
    Abstract: A method is provided for treating an individual for a malarial infection, in particular drug-resistant species of Plasmodium, including administering to the individual in need of such treatment a composition comprising an extract containing an effective amount of one or more anti-malarial di- or tri-terpene compounds. Potent and effective extracts containing the anti-malarial compounds can be derived from Luo Han fruit and Stevia leaves, including combinations of the same, for the purpose of treating and preventing malaria in an inexpensive manner from readily available commodities. In one embodiment, the composition is administered orally in a solid or liquid ingestible form.
    Type: Application
    Filed: September 10, 2011
    Publication date: March 13, 2014
    Applicant: FEBRIS BIO-TECH LIMITED
    Inventors: Garth Selwyn Smith, Lixin Zhang, Huanqin Dai
  • Patent number: 8612691
    Abstract: A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: William E. Speight, Lixin Zhang
  • Patent number: 8612687
    Abstract: A mechanism is provided within a 3D stacked memory organization to spread or stripe cache lines across multiple layers. In an example organization, a 128B cache line takes eight cycles on a 16B-wide bus. Each layer may provide 32B. The first layer uses the first two of the eight transfer cycles to send the first 32B. The next layer sends the next 32B using the next two cycles of the eight transfer cycles, and so forth. The mechanism provides a uniform memory access.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jian Li, William E. Speight, Lixin Zhang
  • Patent number: 8595443
    Abstract: A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Gheorghe C. Cascaval, Balaram Sinharoy, William E. Speight, Lixin Zhang
  • Patent number: 8589665
    Abstract: Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction, the instruction including power/performance tradeoff information associated with the instruction. The mechanisms further operate to determine power/performance tradeoff priorities or criteria, specifying whether power conservation or performance is prioritized with regard to execution of the instruction, based on the power/performance tradeoff information. Moreover, the mechanisms process the instruction in accordance with the power/performance tradeoff priorities or criteria identified based on the power/performance tradeoff information of the instruction.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: John B. Carter, Jian Li, Karthick Rajamani, William E. Speight, Lixin Zhang
  • Patent number: 8563457
    Abstract: 3,4-isoprene-based polymer having high isotacticity can be produced by polymerizing an isoprene compound using a complex represented by the general formula (A) and a catalyst activator: wherein R1 and R2 independently represent an alkyl group, a cyclohexyl group, an aryl group or an aralkyl group; R3 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group, an aralkyl group, an aliphatic, aromatic or cyclic amino group, a phosphino group, a boryl group, an alkylthio or arylthio group, or an alkoxy or aryloxy group; M represents a rare earth element selected from Sc, Y, and La to Lu with promethium (Pm) excluded; Q1 and Q2 independently represent a monoanionic ligand; L represents a neutral Lewis base.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 22, 2013
    Assignee: Riken
    Inventors: Zhaomin Hou, Lixin Zhang
  • Patent number: 8546376
    Abstract: The invention relates to a series of compounds with particular activity as inhibitors of the serine-threonine kinase AKT. Also provided are pharmaceutical compositions comprising same as well as methods for treating cancer.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: October 1, 2013
    Assignee: Almac Discovery Limited
    Inventors: Mark Peter Bell, Timothy Harrison, Sumita Bhattacharyya, James Samuel Shane Rountree, Frank Burkamp, Stephen Price, Calum MacLeod, Richard Leonard Elliott, Phillip Smith, Toby Jonathan Blench, Colin Roderick O'Dowd, Lixin Zhang, Graham Peter Trevitt, Hazel Joan Dyke
  • Patent number: 8543769
    Abstract: A mechanism is provided in a virtual machine monitor for fine grained cache allocation in a shared cache. The mechanism partitions a cache tag into a most significant bit (MSB) portion and a least significant bit (LSB) portion. The MSB portion of the tags is shared among the cache lines in a set. The LSB portion of the tags is private, one per cache line. The mechanism allows software to set the MSB portion of tags in a cache to allocate sets of cache lines. The cache controller determines whether a cache line is locked based on the MSB portion of the tag.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ramakrishnan Rajamony, William E. Speight, Lixin Zhang
  • Patent number: 8540979
    Abstract: Provided are adenoviral vectors for generating an immune response to antigen. The vectors comprise a transcription unit encoding a secretable polypeptide, the polypeptide comprising a secretory signal sequence upstream of a tumor antigen upstream of CD40 ligand, which is missing all or substantially all of the transmembrane domain rendering CD40L secretable. Also provided are methods of generating an immune response against cells expressing a tumor antigen by administering an effective amount of the invention vector. Further provided are methods of generating an immune response against cancer expressing a tumor antigen in an individual by administering an effective amount of the invention vector. Still further provided are methods of generating immunity to infection by human papilloma virus (HPV) by administering an effective amount of the invention vector which enocodes the E6 or E7 protein of HPV. The immunity generated is long term.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 24, 2013
    Assignee: VAXum, LLC
    Inventors: Albert B. Deisseroth, Lixin Zhang
  • Patent number: 8543770
    Abstract: A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: William E. Speight, Lixin Zhang
  • Publication number: 20130241379
    Abstract: A computer case coated with activated carbon is provided to absorb the suspended particulates in the air for purifying the air in the case and at the same time purifying the air in the room. The computer case coated with activated carbon includes a case housing. Inside the case housing a coating of activated carbon is applied. The coating of activated carbon purifies the air and guarantees a clean use environment of computer with better performance and longer service life of hardware and is thus suitable for the application in computer cases.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Applicant: GUANDONG SOHOO TECHNOLOGY CO.,LTD
    Inventor: Lixin ZHANG
  • Patent number: 8495307
    Abstract: Target memory hierarchy specification in a multi-core computer processing system is provided including a system for implementing prefetch instructions. The system includes a first core processor, a dedicated cache corresponding to the first core processor, and a second core processor. The second core processor includes instructions for executing a prefetch instruction that specifies a memory location and the dedicated local cache corresponding to the first core processor. Executing the prefetch instruction includes retrieving data from the memory location and storing the retrieved data on the dedicated local cache corresponding to the first core processor.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tong Chen, Yaoqing Gao, Kevin K. O'Brien, Zehra N. Sura, Lixin Zhang
  • Patent number: 8490065
    Abstract: The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Roch Archambault, Yaoqing Gao, Francis Patrick O'Connell, Robert Brett Tremaine, Michael Edward Wazlowski, Steven Wayne White, Lixin Zhang
  • Patent number: 8482064
    Abstract: A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 9, 2013
    Assignee: Suzhou Poweron IC Design Co., Ltd.
    Inventors: Yangbo Yi, Haisong Li, Qin Wang, Ping Tao, Lixin Zhang
  • Patent number: 8474539
    Abstract: The present disclosure provides an improved design for a pull tube sleeved stress joint and associated pull tube for managing stresses on a catenary riser for a floating offshore structure. The pull tube sleeve stress joint includes at least one sleeve surrounding a length of the pull tube with an annular gap between the sleeve and pull tube and a link ring therebetween. For embodiments having a plurality of sleeves, a first sleeve can be spaced by an annular first gap from the pull tube and coupled thereto with a first ring between the pull tube and the first sleeve, and a second sleeve can be spaced by an annular second gap from the first sleeve and coupled thereto with a second ring between the first sleeve and the second sleeve. Both pull tube and sleeves can be made with regular pipe segments welded together with regular girth welds.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 2, 2013
    Assignee: Technip France
    Inventors: Michael Y. H. Luo, Bob Lixin Zhang, Shih-Hsiao Mark Chang
  • Patent number: 8458408
    Abstract: A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: William E. Speight, Lixin Zhang
  • Publication number: 20130116243
    Abstract: The invention relates to a series of compounds with particular activity as inhibitors of the serine-threonine kinase AKT. Also provided are pharmaceutical compositions comprising same as well as methods for treating cancer.
    Type: Application
    Filed: December 23, 2010
    Publication date: May 9, 2013
    Applicant: ALMAC DISCOVERY LIMITED
    Inventors: Lixin Zhang, Graham Peter Trevitt, Hugues Miel, Frank Burkamp, Timothy Harrison, Andrew John Wilkinson, Charles-Henry Fabritius