Abstract: A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.

Abstract: Embodiments of the present disclosure provide an integrated circuit including multiple source/drain physical dimensions for the same type devices co-exist in the same chip. Some embodiments provide methods for modulating source/drain physical dimension to fine-tune parasite capacitance, such as parasite capacitance between gate and drain Cgd, and resistance, such as resistance for source/drain contact Rc in analog or RF (radio frequency) devices.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes an active region, and the active region includes a fin extending over a substrate, a first dummy gate electrode layer disposed over the fin, a second dummy gate electrode layer adjacent the first dummy gate electrode layer, a third dummy gate electrode layer disposed over the fin and a fourth dummy gate electrode layer adjacent the third dummy gate electrode layer. The second and third dummy gate electrode layers are disposed between the first and fourth dummy gate electrode layers. The active region further includes an active gate electrode layer disposed over the fin, and the active gate electrode layer is disposed between the second and third dummy gate electrode layers.

Abstract: A method of manufacturing an isolation structure includes: preparing a substrate having a metal electrode pattern; disposing a two-terminal micro device on the substrate, such that a bottom electrode of the two-terminal micro device contacts the metal electrode pattern; forming a photoresist layer to cover the substrate and the two-terminal micro device, in which the photoresist layer has an upper portion and a lateral portion respectively on a top side and a lateral side of the two-terminal micro device, and a height difference between the upper and lateral portions is less than half of the device height; exposing the photoresist layer with a low dose to adjust a developing rate of the photoresist layer; and developing a top side of the exposed photoresist layer at least until a top electrode on the top side of the two-terminal micro device is exposed by the developed photoresist layer.

Abstract: A method of manufacturing an isolation structure includes: preparing a substrate with a micro diode having a top electrode and a bottom electrode that is bonded on a bottom conduction pad on the substrate, in which a passivation layer covers the top electrode and a sidewall of the micro diode; forming a photoresist layer to cover the substrate and the micro diode, in which the photoresist layer has upper and lateral portions respectively on top and lateral sides of the micro diode and having a height difference less than half of a device height of the micro diode; exposing the photoresist layer with a low dose less than half of a full dose of the photoresist layer; eroding the exposed photoresist layer until a top surface of the passivation layer is exposed by the photoresist layer; and removing the passivation layer to expose the top electrode.

Abstract: A micro light-emitting diode device includes a substrate, a micro light-emitting diode, an isolation layer, and a cathode transparent electrode. The micro light-emitting diode is disposed on the substrate and includes a p-type III-nitride layer, n-type III-nitride layers with a layer number of m sequentially stacked above the p-type III-nitride layer, and an active layer between the p-type III-nitride layer and the n-type III-nitride layers. m is an integer greater than two. A top layer and a next layer in contact with each other of the n-type III-nitride layers contain aluminum. The isolation layer is on the substrate and surrounds the micro light-emitting diode. The cathode transparent electrode is at least partially in contact with a top surface of the top layer. A refractive index of the top layer is smaller than a refractive index of the next layer.

Abstract: A micro light-emitting diode device includes a substrate, a micro light-emitting diode, and a transparent top electrode. The micro light-emitting diode is disposed on the substrate and includes a p-type GaN layer, an n-type GaN layer above the p-type GaN layer, an n-doped AlxGa(1?x)N layer above and in contact with the n-type GaN layer, and an active layer between the p-type GaN layer and the n-type GaN layer. x is equal to or greater than 0.02 and smaller than 1. The transparent top electrode covers and is in contact with the n-doped AlxGa(1?x)N layer. A refractive index of the n-doped AlxGa(1?x)N layer is smaller than a refractive index of the n-type GaN layer. A sum of the thicknesses of the n-type GaN layer and the n-doped AlxGa(1?x)N layer is greater than a sum of the thicknesses of the active layer and the p-type GaN layer.

Abstract: A micro light-emitting diode device includes a substrate, a micro light-emitting diode, and a transparent top electrode. The micro light-emitting diode is disposed on the substrate and includes a p-type GaN layer, an n-type III-nitride layer above the p-type GaN layer, an n-doped AlxGayIn(1-x-y)N layer above and in contact with the n-type III-nitride layer, and an active layer between the p-type GaN layer and the n-type III-nitride layer. x is equal to or greater than about 0.02. The transparent top electrode covers and is in contact with the n-doped AlxGayIn(1-x-y)N layer. A refractive index of the n-doped AlxGayIn(1-x-y)N layer is smaller than a refractive index of the n-type III-nitride layer. A sum of the thicknesses of the n-type III-nitride layer and the n-doped AlxGayIn(1-x-y)N layer is greater than a sum of the thicknesses of the active layer and the p-type GaN layer.

Abstract: A micro light-emitting diode device includes a substrate, a micro light-emitting diode, and a cathode transparent electrode. The micro light-emitting diode is disposed on the substrate and includes a p-type III-nitride layer, a first n-type III-nitride layer above the p-type III-nitride layer, a second n-type III-nitride layer above the first n-type III-nitride layer, and an active layer between the p-type and first n-type III-nitride layers. The second n-type III-nitride layer contains aluminum and has top and bottom surfaces. A refractive index of the second n-type III-nitride layer is smaller than a refractive index of the first n-type III-nitride layer and varies in a monotonically non-decreasing manner from the top surface. The refractive index of the second n-type III-nitride layer is larger at the bottom surface than at the top surface. The cathode transparent electrode is in contact with the top surface.

Abstract: A micro light-emitting diode device includes a substrate, a micro light-emitting diode, and a transparent top electrode. The micro light-emitting diode is disposed on the substrate and includes a p-type GaN layer, an n-type GaN layer above the p-type GaN layer, an n-doped InxAl(1-x)N layer above and in contact with the n-type GaN layer, and an active layer between the p-type GaN layer and the n-type GaN layer. x is a positive number smaller than 0.5. The transparent top electrode covers and is in contact with the n-doped InxAl(1-x)N layer. A refractive index of the n-doped InxAl(1-x)N layer is smaller than a refractive index of the n-type GaN layer. A sum of the thicknesses of the n-type GaN layer and the n-doped InxAl(1-x)N layer is greater than a sum of the thicknesses of the active layer and the p-type GaN layer.

Abstract: A method of manufacturing micro devices includes: preparing a GaN-based epitaxial structure including a p-type GaN layer, a n-type GaN layer on the p-type GaN layer, and an undoped GaN layer on the n-type GaN layer; forming a photoresist layer on the GaN-based epitaxial structure with the undoped GaN layer contacting the photoresist layer; patterning the photoresist layer; performing a plasma etching process to the GaN-based epitaxial structure through the patterned photoresist layer until the patterned photoresist layer is completely removed, such that a plurality of mesas are formed on the etched GaN-based epitaxial structure, in which a height of the mesas is at least 1.0 ?m; and continuing to perform the plasma etching process until the undoped GaN layer is completely removed and the etched GaN-based epitaxial structure is cut into a plurality of micro devices.

Abstract: A method of manufacturing a structure having anodized parts includes: forming a bottom metal layer on a substrate; forming a top metal layer on the bottom metal layer; forming a mask layer on the top metal layer to expose a portion of a top surface of the top metal layer; etching the top metal layer through the mask layer until a top surface of the bottom metal layer is exposed, wherein an etch selectivity of the top metal layer and the bottom metal layer is greater than 2.0; anodizing the bottom metal layer through the mask layer to form an anodized segment; and removing the mask layer after the anodizing.

Abstract: A structure having multi-dielectric layers includes a conduction channel, a sidewall oxide dielectric structure, and a top oxide dielectric structure. The conduction channel contains aluminum. The sidewall oxide dielectric structure is in contact with a side surface of the conduction channel and has a first effective permittivity. The top oxide dielectric structure is in contact with a top surface of the conduction channel and a top surface of the sidewall oxide dielectric structure and has a second effective permittivity. The second effective permittivity is greater than the first effective permittivity.

Abstract: A method of forming an electrode with multi-dielectric layers includes: forming a metal pattern on a substrate, in which the metal pattern includes a first metal film on the substrate and a second metal film on a top surface of the first metal film, and the first and second metal films have different metal compositions; and anodizing the metal pattern in a liquid electrolyte to form a covering anodized portion which covers an unanodized portion, in which the covering anodized portion includes a sidewall oxide dielectric structure and a top oxide dielectric structure, the sidewall oxide dielectric structure is in contact with a side surface of the unanodized portion, the top oxide dielectric structure is in contact with top surfaces of the unanodized portion and the sidewall oxide dielectric structure, and the sidewall and top oxide dielectric structures have different effective permittivities.

Abstract: A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.

Abstract: A structure having multi-dielectric layers includes a conduction channel, a sidewall oxide dielectric structure, and a top oxide dielectric structure. The conduction channel contains aluminum. The sidewall oxide dielectric structure is in contact with a side surface of the conduction channel and has a first effective permittivity. The top oxide dielectric structure is in contact with a top surface of the conduction channel and a top surface of the sidewall oxide dielectric structure and has a second effective permittivity. A material of the top oxide dielectric structure includes silicon. The first effective permittivity is greater than the second effective permittivity.

Abstract: A method of manufacturing a thin-film transistor TFT with a metal cross over structure includes: etching the first metal layer through a first patterned photoresist to form a gate electrode and a lower metal pattern; anodizing the first metal layer; removing the first patterned photoresist; depositing a semiconductor layer on the etched first metal layer; depositing a second metal layer on the semiconductor layer; anodizing the second metal layer through a second patterned photoresist to form an anodized segment; and etching the second metal layer through the second patterned photoresist to form first and second upper metal patterns, in which the first upper metal pattern has drain and source electrodes connected to the anodized segment and electrically isolated from each other by the anodized segment, and the second upper metal pattern forms a metal cross over structure with the lower metal pattern.

Abstract: A method of manufacturing a structure having an electrode and an anodized part includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, in which the top patterned photoresist has a first mask portion and a second mask portion thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after the anodizing; and etching the top metal layer through the top patterned photoresist after the removing the first mask portion to form a top metal pattern.

Abstract: A method of manufacturing a structure having an electrode and an anodized part includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, in which the top patterned photoresist has a first mask portion and a second mask portion thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after the anodizing; etching the top metal layer through the top patterned photoresist after the removing the first mask portion to form a top metal pattern; and reflowing the top patterned photoresist after the anodizing and before the etching.

Abstract: A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.