Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

Abstract: A control method of an image signal processor for an artificial neural network may be configured to include a step of acquiring an image, a step of determining at least one image characteristic data corresponding to the image, and a step of determining an image correction parameter (SFR preset) for improving an inference accuracy of an artificial neural network model based on the at least one of image characteristic data and an inference accuracy profile of an artificial neural network model.

Abstract: A neural processing unit may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of groups of processing elements (PEs) including a plurality of PEs; a second circuit arranged to output a plurality of clock signals to the first circuit; a third circuit configured to measure a ratio of peak power and average power of at least the first circuit; and a fourth circuit, arranged to dynamically calibrate a phase of at least one of the plurality of clock signals of the second circuit based on the ratio of peak power and average power measured in the third circuit.

Abstract: A computation method for the binary neural network is performed on a computing device that includes one or more processors and a memory storing one or more programs executed by the one or more processors, and includes generating a fully connected graph based on output channels of a convolutional layer of a binary neural network, extracting a minimum spanning tree from the fully connected graph, and re-arranging an order of computations between respective output channels based on the minimum spanning tree.

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

Abstract: A neural network processing unit (NPU) includes a processing element array, a SRAM memory configured to store at least one data of the artificial neural network model processed in the processing element array; and an NPU scheduler configured to control the processing element array and the SRAM memory based on predefined operation order information of the artificial neural network model processed by the processing element array and the NPU scheduler is configured to reuse a memory address value in which an operation value of a first layer of a first scheduling is stored as a memory address value corresponding to an input data of a second layer of a second scheduling, which is a next scheduling of the first scheduling.

Abstract: A neural processing unit (NPU) is proposed. The NPU may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of processing elements (PE) groups including a plurality of PEs, and a second circuit configured to operate as a clock divider configured to generate a plurality of clock signals having different phases, respectively, by dividing a source clock signal and provide the plurality of clock signals to the plurality of PE groups. A first clock signal of the plurality of clock signals may be provided to a first PE group of the plurality of PE groups, and a second clock signal of the plurality of clock signals may be provided to a second PE group of the plurality of PE groups.

Abstract: A method performs a plurality of operations on an artificial neural network (ANN). The plurality of operations includes storing in at least one memory a set of weights, at least a portion of a first batch channel of a plurality of batch channels, and at least a portion of a second batch channel of the plurality of batch channels; and calculating the at least a portion of the first batch channel and the at least a portion of the second batch channel by the set of weights. A batch mode, configured to process a plurality of input channels, can determine the operation sequence in which the on-chip memory and/or internal memory stores and computes the parameters of the ANN. Even if the number of input channels increases, processing may be performed with one neural processing unit including a memory configured in consideration of a plurality of input channels.

Abstract: An artificial neural network memory system includes at least one processor configured to generate a data access request corresponding to an artificial neural network operation; and at least one artificial neural network memory controller configured to sequentially record the data access request to generate an artificial neural network data locality pattern of the artificial neural network operation and generate an advance data access request which predicts a next data access request of the data access request generated by the at least one processor based on the artificial neural network data locality pattern.

Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.

Abstract: A learning model creation method for performing a specific function for an electronic device includes: preparing big data for training an artificial neural network including, in pairs, sensing data received from a random sensing data generation unit for sensing human behaviors and specific function performance determination data for determining whether to perform a specific function of an electronic device with respect to the sensing data; preparing an artificial neural network model, and association parameters between the nodes of the input layer and the nodes of the output layer, and calculates inputs of the sensing data for the nodes of the input layer in order to output the specific function performance determination data from the nodes of the output layer; and repeatedly performing a process of inputting the sensing data included in the prepared big data into the nodes of the input layer.

Abstract: A neural processing unit (NPU) mounted on a movable device for detecting object is provided. The NPU may comprise a plurality of processing elements (PEs), configured to process an operation of a first artificial neural network model (ANN) and an operation of a second ANN different from the first ANN; a memory configured to store a portion of a data of the first ANN and the second ANN; and a controller configured to control the PEs and the memory to selectively perform a convolution operation of the first ANN or the second ANN based on a determination data, wherein the determination data may include an object detection performance data of the first ANN and the second ANN, respectively.

Abstract: According to an example of the present disclosure, a system is provided.

Abstract: A method for stabilizing an image based on artificial intelligence includes acquiring tremor detection data with respect to the image, the tremor detection data acquired from two or more sensors; outputting stabilization data for compensating for an image shaking, the stabilization data outputted using an artificial neural network (ANN) model trained to output the stabilization data based on the tremor detection data; and compensating for the image shaking using the stabilization data. A camera module includes a lens; an image sensor to output an image captured through the lens; two or more sensors to output tremor detection data with respect to the image; a controller to output stabilization data based on the tremor detection data using an ANN model; and a stabilization unit to compensate for an image shaking using the stabilization data. The ANN model is trained to output the stabilization data based on the tremor detection data.

Abstract: A method performs a plurality of operations on an artificial neural network (ANN). The plurality of operations includes storing in at least one memory a set of weights, at least a portion of a first batch channel of a plurality of batch channels, and at least a portion of a second batch channel of the plurality of batch channels; and calculating the at least a portion of the first batch channel and the at least a portion of the second batch channel by the set of weights. A batch mode, configured to process a plurality of input channels, can determine the operation sequence in which the on-chip memory and/or internal memory stores and computes the parameters of the ANN. Even if the number of input channels increases, processing may be performed with one neural processing unit including a memory configured in consideration of a plurality of input channels.

Abstract: A method for evaluating artificial neural network (ANN) model's processing performance comprising selecting a type and a number of at least one neural processing unit (NPU) for processing performance evaluation for a user, selecting at least one of a plurality of compilation options for an artificial neural network (ANN) model to be processed by the at least one NPU which is selected, uploading the ANN model and at least one evaluation dataset to be processed by the at least one NPU which is selected, compiling the ANN model according to the at least one of the plurality of compilation options which is selected, and reporting a processing performance by processing the ANN model on the at least one NPU which is selected.

Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

Abstract: A system may comprise a neural processing unit (NPU) including a plurality of processing elements (PEs) capable of performing computations for at least one artificial neural network (ANN) model; and a switching circuit. The switching circuit may be configured to select one clock signal among a plurality of clock signals having different frequencies, and supply the selected clock signal to the NPU. The one clock signal may be selected based on a utilization rate of the plurality of PEs for a particular layer among a plurality of layers of the at least one ANN model.

Abstract: According to an example of the present disclosure, a system is provided. A system may include a processor configured to output a memory control signal including an artificial neural network data locality, and a memory controller configured to receive the memory control signal from the processor and control a main memory in which data of an artificial neural network model corresponding to the artificial neural network data locality, is stored.