Abstract: An example three-dimensional (3-D) memory array includes a substrate material including a plurality of conductive contacts arranged in a staggered pattern and a plurality of planes of a conductive material separated from one another by a first insulation material formed on the substrate material. Each of the plurality of planes of the conductive material includes a plurality of recesses formed therein. A second insulation material is formed in a serpentine shape through the insulation material and the conductive material. A plurality of conductive pillars are arranged to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate and each respective conductive pillar is coupled to a different respective one of the conductive contacts. A chalcogenide material is formed in the plurality of recesses such that the chalcogenide material in each respective recess is formed partially around one of the plurality of conductive pillars.

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure.

Abstract: An example three-dimensional (3-D) memory array includes a substrate material including a plurality of conductive contacts arranged in a staggered pattern and a plurality of planes of a conductive material separated from one another by a first insulation material formed on the substrate material. Each of the plurality of planes of the conductive material includes a plurality of recesses formed therein. A second insulation material is formed in a serpentine shape through the insulation material and the conductive material. A plurality of conductive pillars are arranged to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate and each respective conductive pillar is coupled to a different respective one of the conductive contacts. A chalcogenide material is formed in the plurality of recesses such that the chalcogenide material in each respective recess is formed partially around one of the plurality of conductive pillars.

Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

Abstract: Methods, systems, and devices for composite electrode material chemistry are described. A memory device may include an access line, a storage element comprising chalcogenide, and an electrode coupled with the memory element and the access line. The electrode may be made of a composition of a first material doped with a second material. The second material may include a tantalum-carbon compound. In some cases, the second may be operable to be chemically inert with the storage element. The second material may include a thermally stable electrical resistivity and a lower resistance to signals communicated between the access line and the storage element across a range of operating temperatures of the storage element as compared with a resistance of the first material.

Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure.

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure.

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.

Abstract: Methods, systems, and devices for memory device with a split pillar architecture are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars and cell material may be divided to form a first and second storage components and first and second pillars.

Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.

Abstract: Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.

Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.