Abstract: A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure.

Abstract: The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value.

Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.

Abstract: A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

Abstract: The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.

Abstract: The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.

Abstract: A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver.

Abstract: A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for moving from a first position to a second position for reading out a charge stored within the capacitor or for writing the charge to the capacitor. A method is also disclosed for fabricating each MEM memory cell of the MEMRAM array.

Abstract: A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.

Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

Abstract: An SRAM system is provided having an array of SRAM cells receiving a first power voltage. The SRAM system includes at least one circuit receiving a first power voltage, and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit of the system. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. Furthermore, a method is provided for providing a power supply voltage to at least one circuit of a system. The method includes the steps of providing a first power supply voltage to the at least one circuit of the system, and providing a second power supply voltage to at least one selected circuit of the at least one circuit.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation. The data communication system further includes a central data path in data communication for transferring data with the plurality of data paths.

Abstract: A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver.

Abstract: A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80% Al2O3.

Abstract: A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated.