Patents by Inventor Lu Chang

Lu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240148124
    Abstract: A nail tool for removing tissue in a nail groove is adapted for extending into the nail groove to remove the tissue. The nail tool includes a rod body assembly and a tissue removing member. The rod body assembly extends in a front-rear direction and includes a rod body. The rod body has a front end portion, and a rear end portion that is located opposite to the front end portion. The tissue removing member is connected to the front end portion of the rod body, and includes a seat body and a removing section that is located at a front end of the seat body. The seat body has a groove wall that defines an accommodating groove. The removing section has a rough surface. The groove wall is adapted to widen the nail groove to allow the rough surface to remove the tissue.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Inventor: Ching-Lu CHANG
  • Patent number: 11978669
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240145575
    Abstract: A semiconductor device includes a substrate, a channel layer, a first barrier layer, a source/drain contact, and a gate layer. The channel layer is on the substrate. The first barrier layer is on the channel layer and the thickness of the first barrier layer is less than 6 nm. The source/drain contact is on the first barrier layer and is directly contact with the first barrier layer. The gate layer is over the first barrier layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: May 2, 2024
    Inventors: Edward Yi CHANG, You-Chen WENG, Min-Lu KAO
  • Patent number: 11974104
    Abstract: A linearity compensation method for a sound producing device (SPD) includes steps of: applying a test signal on a first SPD; obtaining an acoustic measurement result generated from the first SPD according to the test signal; generating a compensation curve according to the acoustic measurement result; and performing a linearity compensation operation on a second SPD according to the compensation curve.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 30, 2024
    Assignee: xMEMS Labs, Inc.
    Inventors: Jemm Yue Liang, Yanchen Lu, Hao-Hsin Chang
  • Publication number: 20240136432
    Abstract: A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: April 25, 2024
    Applicants: National Yang Ming Chiao Tung University, National Chung-Shan Institute of Science and Technology
    Inventors: Edward Yi CHANG, You-Chen WENG, Min-Lu KAO
  • Publication number: 20240136422
    Abstract: A high electron mobility transistor and a method for fabricating the same is disclosed. Firstly, a lattice matching layer, a channel layer, and an AlGaN layer are sequentially formed on a growth substrate. The AlGaN layer includes a first area, a second area, and a third area, wherein the second area is located between the first area and the third area. Then, an insulation block is formed on the second area of the AlGaN layer and two GaN blocks are respectively formed on the first area and the third area of the AlGaN layer. Two InAlGaN blocks are respectively formed on the GaN blocks and the insulation block is removed. Finally, a gate is formed to interfere the second area of the AlGaN layer and a source and a drain are respectively formed on the InAlGaN blocks.
    Type: Application
    Filed: January 13, 2023
    Publication date: April 25, 2024
    Applicants: National Yang Ming Chiao Tung University, National Chung-Shan Institute of Science and Technology
    Inventors: Edward Yi CHANG, You-Chen WENG, Min-Lu Kao
  • Publication number: 20240126729
    Abstract: JSON Duality Views are object views that return JDV objects. JDV objects are virtual because they are not stored in a database as JSON objects. Rather, JDV objects are stored in shredded form across tables and table attributes (e.g. columns) and returned by a DBMS in response to database commands that request a JDV object from a JSON Duality View. Through JSON Duality Views, changes to the state of a JDV object may be specified at the level of a JDV object. JDV objects are updated in a database using optimistic lock.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Inventors: ZHEN HUA LIU, JUAN R. LOAIZA, SUNDEEP ABRAHAM, SHUBHA BOSE, HUI JOE CHANG, SHASHANK GUGNANI, BEDA CHRISTOPH HAMMERSCHMIDT, TIRTHANKAR LAHIRI, YING LU, DOUGLAS JAMES MCMAHON, AUROSISH MISHRA, AJIT MYLAVARAPU, SUKHADA PENDSE, ANANTH RAGHAVAN
  • Publication number: 20240126743
    Abstract: JSON Duality Views are object views that return JDV objects. JDV objects are virtual because they are not stored in a database as JSON objects. Rather, JDV objects are stored in shredded form across tables and table attributes (e.g. columns) and returned by a DBMS in response to database commands that request a JDV object from a JSON Duality View. Through JSON Duality Views, changes to the state of a JDV object may be specified at the level of a JDV object. JDV objects are updated in a database using optimistic lock.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Inventors: ZHEN HUA LIU, JUAN R. LOAIZA, SUNDEEP ABRAHAM, SHUBHA BOSE, HUI JOE CHANG, SHASHANK GUGNANI, BEDA CHRISTOPH HAMMERSCHMIDT, TIRTHANKAR LAHIRI, YING LU, DOUGLAS JAMES MCMAHON, AUROSISH MISHRA, AJIT MYLAVARAPU, SUKHADA PENDSE, ANANTH RAGHAVAN
  • Publication number: 20240126728
    Abstract: JSON Duality Views are object views that return JDV objects. JDV objects are virtual because they are not stored in a database as JSON objects. Rather, JDV objects are stored in shredded form across tables and table attributes (e.g. columns) and returned by a DBMS in response to database commands that request a JDV object from a JSON Duality View. Through JSON Duality Views, changes to the state of a JDV object may be specified at the level of a JDV object. JDV objects are updated in a database using optimistic lock.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Inventors: ZHEN HUA LIU, JUAN R. LOAIZA, SUNDEEP ABRAHAM, SHUBHA BOSE, HUI JOE CHANG, SHASHANK GUGNANI, BEDA CHRISTOPH HAMMERSCHMIDT, TIRTHANKAR LAHIRI, YING LU, DOUGLAS JAMES MCMAHON, AUROSISH MISHRA, AJIT MYLAVARAPU, SUKHADA PENDSE, ANANTH RAGHAVAN
  • Patent number: 11960167
    Abstract: A backplane includes: a substrate including a circuit structure layer, a first reflective layer disposed on a bearing surface of the substrate, a plurality of light-emitting diode chips, and a plurality of optical structures. The first reflective layer includes a plurality of through holes spaced apart. A light-emitting diode chip in the plurality of light-emitting diode chips is located in one of the plurality of through holes. The plurality of light-emitting diode chips are electrically connected to the circuit structure layer. The circuit structure layer is configured to drive the plurality of light-emitting diode chips to emit light. An optical structure in the plurality of optical structures covers the light-emitting diode chip, a light incident surface of the optical structure is in contact with a light exit surface of the light-emitting diode chip, and a light exit surface of the optical structure is a curved surface.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: April 16, 2024
    Assignees: BOE MLED Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pei Li, Haiwei Sun, Ming Zhai, Lu Yu, Kangle Chang, Jinpeng Li, Pengjun Cao, Yutao Hao, Shubai Zhang, Shuo Wang, Pei Qin, Zewen Gao, Yali Zhang
  • Patent number: 11960870
    Abstract: Methods, systems, and computer program products for container image management are disclosed. In a method, a first group of operations that are performed in respective layers in a base image are obtained. A second group of operations that are performed in respective layers not comprised in the base image are obtained. The second group of operations are optimized based on a comparison between the first and second groups of operations. A destination container image is generated based on the optimized second group of operations and the base image.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Lu Yan Li, Zhan Peng Huo, Fei Tan, Jiu Chang Du
  • Patent number: 11963405
    Abstract: A display and a display panel are provided. An additional VDD wire is arranged in an irregular-shaped region. The VDD wire is connected to a pixel arranged in the irregular-shaped region through a plurality of connection wires, such that the display may have a narrow side edge, and at the same time, a difference between impedances of the irregular-shaped region and a regular-shaped display region may not be large, and a display region may not be split.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 16, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Miao Chang, Weilong Li, Lu Zhang, Siming Hu, Zhenzhen Han
  • Publication number: 20240113259
    Abstract: A light-emitting device includes a semiconductor epitaxial structure including a first semiconductor layer, an active layer, and a second semiconductor layer, and having holes; a first insulation layer disposed on the semiconductor epitaxial structure and having first and second grooves; a first pad electrically connected to the first semiconductor layer through the first grooves; and a second pad electrically connected to the second semiconductor layer through the second grooves. A projection of the first pad does not overlap projections of the holes. A projection of the second pad does not overlap the projections of the holes. The first pad includes a first pad connection portion and first pad extension portions; the second pad includes a second pad connection portion and second pad extension portions. Projections of the second grooves fall between projections of the first and second pad extension portions. Two other aspects of the light-emitting device are also provided.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Xiushan ZHU, Qi JING, Yan LI, Xiaoliang LIU, Zhilong LU, Chunhsien LEE, Chi-Ming TSAI, Juchin TU, Chung-Ying CHANG
  • Publication number: 20240096757
    Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Publication number: 20240096961
    Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Shih-Chuan CHIU, Tien-Lu LIN, Yu-Ming LIN, Chia-Hao CHANG, Chih-Hao WANG, Jia-Chuan YOU
  • Publication number: 20240099055
    Abstract: A layered semiconductor device comprises at least one particle structure disposed on an underlying layer that comprises a particle material in contact with a contact material selected from: a seed material, a co-deposited dielectric material and/or at least one patterning material. A method for controllably selecting formation of the at least one particle structure on an underlying layer during manufacture of the device comprises depositing at least one layer, including the underlying layer, and exposing its surface to a flux of a particle material such that it comes into contact with the contact material, and coalesces to dispose the at least one particle structure on the underlying layer.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 21, 2024
    Applicant: OTI Lumionics Inc.
    Inventors: Michael HELANDER, Zhibin WANG, Yi-Lu CHANG, Qi WANG
  • Publication number: 20240084394
    Abstract: The invention relates to methods and compositions for detecting colorectal cancer and colorectal polyps by measurement of metabolites in bodily fluids such as urine, including diacetylspermine and kynurenine.
    Type: Application
    Filed: November 3, 2023
    Publication date: March 14, 2024
    Applicant: Metabolomic Technologies Inc.
    Inventors: Lu DENG, David Chang
  • Patent number: 11927444
    Abstract: Disclosed is a chip-level resonant acousto-optic coupling solid-state wave gyroscope based on MEMS technology. A surface acoustic progressive wave mode sensitive structure and a micro-ring resonant cavity optical detection structure are combined in the gyroscope. Through acousto-optic effect, mechanical strain of the device crystal caused by wave vibration of a primary surface acoustic wave and a secondary surface acoustic wave caused by Coriolis force is converted into a variation in the refractive index of an optical waveguide etched on the device, so that the optical signal transmitted in the waveguide diffracts, thereby generating frequency modulation. Meanwhile, a micro-ring resonant cavity using the resonance principle peels off the frequency change introduced by the primary surface acoustic wave, and obtains an output signal containing external angular velocity information.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: March 12, 2024
    Assignee: NORTHWESTERN POLYTECHNICAL UNIVERSITY
    Inventors: Honglong Chang, Lu Tian, Qiang Shen
  • Patent number: 11924965
    Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Jian-Hong Lin, Shu-Yuan Ku, Wei-Cheng Liu, Yinlung Lu, Jun He
  • Patent number: D1016698
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Foxtron Vehicle Technologies Co., Ltd.
    Inventors: Tse-Min Cheng, Ming-Chang Lin, Yuan-Jie He, Chiao-Chi Lin, Lu-Han Lee