Abstract: A multi-function device includes a machine base, a plurality of horizontal bars, at least one gantry, a plurality of processing units and at least one first conveying uni. The horizontal bars are disposed at the top of the machine base. The gantry is disposed on the machine base and disposed over the horizontal bars. The processing unit is disposed on the horizontal bars and the gantry. The first conveying unit is disposed on the machine base. Each processing unit is a processing device capable of being replaced according to actual requirements, such as a soldering flux device, a soldering device, a sucking device, a glue dipping device, a glue dispensing device, a detecting device, a cleaning device or other processing devices. The present invention can integrate different types of manufacturing devices into one device, and the quantities of the horizontal bars and the modules thereof are not limited.

Abstract: Apparatus and methods for deployment of fixtures. The apparatus may include a system for controlling deployed fixtures. The system may receive user commands different devices in different formats. The fixtures may be independently addressable. The fixtures may be magnetically supported by a fixture support. A brace may join two or more fixture supports without reducing space available to support fixtures. The brace may join a fixture support to a fixture support accessory. An accessory may include a variable-angle junction. The fixture may include articulating joints for controlling the direction of a beam. The fixture may include a lens having an electrically controllable beam spread angle. The fixture may be stowable in the fixture support. The fixture may be slidable along a cord to adjust a height of the fixture. The fixture may include an extendable ring. The system may coordinate motions of the fixtures to follow a target. The fixture may include an elongated board.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.

Abstract: An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.

Abstract: A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.

Abstract: A method for preparing anisotropic cellulose-based hydrogel is provided. The method comprises ammoniating the dialdehyde cellulose obtained by oxidizing cellulose using sodium periodate to obtain ammoniated cellulose derivatives; performing Schiff reaction using the ammoniated cellulose derivatives and dopamine to obtain cellulose-based nanosheets; depositing Fe3O4 nanoparticles on a surface of the cellulose-based nanosheets by a deposition method to obtain magnetic cellulose-based nanosheets; and forming the anisotropic cellulose-based hydrogel using the magnetic cellulose-based nanosheets by a polymerization method.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first dielectric layer, a first gate, a second dielectric layer, and a second gate. The first dielectric layer is located on the substrate. The first gate is located on the first dielectric layer. The second dielectric layer is located on the substrate. The second gate is located on the second dielectric layer. A bottom surface of the second gate and a bottom surface of the first gate are located on different planes.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer. The semiconductor device structure also includes an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer. In addition, the semiconductor device structure includes gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a pair of source/drain features formed in a semiconductor substrate and a gate stack formed over a portion of the semiconductor substrate that is between the pair of source/drain features. The semiconductor device structure also includes gate spacers extend along opposing sidewalls of the gate stack and protrude above an upper surface of the gate stack. Additionally, the semiconductor device structure includes a first capping layer formed over the gate stack and spaced apart from the upper surface of the gate stack by a gap. Opposing sidewalls of the first capping layer are covered by portions of the gate spacers that protrude above the upper surface of the gate stack.

Abstract: Bimetal oxide catalyst and methods, a method comprises: mixing and grinding to obtain a mixture comprising a manganese salt (a), at least one of other metal salt (b), and an additive (c), wherein the other metal salt comprises at least one of a copper salt, a cobalt salt, a cerium salt, an iron salt, or a nickel salt, and the additive comprises at least one of polyol or organic acid, and calcining the mixture to obtain the bimetal oxide catalyst.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: An autoinducer-2 (AI-2) molecular response-based starting element and an Escherichia coli (E. coli) dynamic regulation system and method constructed thereby are provided. A cell density-dependent starting element PJ23119-LsrR-PlsrA based on an AI-2 molecular response is constructed. The element can be used to self-induce the expression of dCpf1, and crRNAs of different target genes are further assembled, such that the self-inducible element can be used for dCpf1-CRP to achieve the dynamic regulation of genes in a synthesis pathway. In the present disclosure, vectors pACYDuet-PJ23119-LsrR-PlsrA-dCpf1-CRP, pRSFDuet-GFP-mCherry, and pETDuet-crRNA can be constructed to simultaneously achieve the transcriptional activation and inhibition of different genes. The construction method of recombinant E. coli in the present disclosure is simple and has promising application prospects.