Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

Abstract: It is an object of the present invention to diagnose image quality of a print image without using an open communication network and output the print image, a diagnosis result of image quality, and information of the print parameters while avoiding disclosure of confidential information to users. A test print control portion causes a print device to execute a test print process to form a test image on a sheet. An image quality diagnosis portion diagnoses image quality of the test image included in the image read by an image reading device. A code image generating portion generates a code image that represents information of print parameters adopted in the test print process. An output control portion causes an output device to output a diagnosis image that includes an image representing a diagnosis result of image quality of the test image, and the code image.

Abstract: A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Abstract: It is an object of the present invention to diagnose image quality of a print image without using an open communication network and output the print image, a diagnosis result of image quality, and information of the print parameters while avoiding disclosure of confidential information to users. A test print control portion causes a print device to execute a test print process to form a test image on a sheet. An image quality diagnosis portion diagnoses image quality of the test image included in the image read by an image reading device. A code image generating portion generates a code image that represents information of print parameters adopted in the test print process. An output control portion causes an output device to output a diagnosis image that includes an image representing a diagnosis result of image quality of the test image, and the code image.

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, a gate spacer disposed on a sidewall of the metal gate structure, an source/drain contact disposed over the semiconductor substrate and separated from the metal gate structure by the gate spacer, and a contact feature coupling the metal gate structure to the source/drain contact. The contact feature may be configured to include a dielectric layer disposed on a metal layer, where the dielectric layer and the metal layer are defined by continuous sidewalls.

Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Abstract: The present disclosure provides a method for semiconductor fabrication. The method includes epitaxially growing source/drain feature on a fin; forming a silicide layer over the epitaxial source/drain feature; forming a seed metal layer on the silicide layer; forming a contact metal layer over the seed metal layer using a bottom-up growth approach; and depositing a fill metal layer over the contact metal layer.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.

Abstract: The present disclosure discloses a method for preparing dual-sensitive cellulose-based aerogel. The DAC (Dialdehyde cellulose), the DAC/PDMAEMA (poly-2-(dimethylamino)ethyl methacrylate) copolymer, the DAC/PDMAEMA/PEI (Polyethylenimine) copolymer are serially prepared, was freeze-dried to obtain a product. The product is the dual-sensitive cellulose-based aerogel, a cumulative adsorption capacity of the dual-sensitive cellulose-based aerogel is 250 mg/g, and a cumulative release amount of the dual-sensitive cellulose-based aerogel in 0.05 mol/L NaH2PO4 (pH=3-8), 0.2% NaCl (pH<3), or NaOH (pH>8) is 63-90%.

Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.

Abstract: A wafer etching apparatus and a method for controlling an etch bath of a wafer is provided. The wafer etching apparatus includes an etching tank comprising an etch bath, an etch bath recycle system connected to the etching tank, a real time monitor (RTM) system connected to the etching tank, and a control system coupled with the RTM system and the etch bath recycle system. The wafer etching apparatus and the method for controlling an etch bath of the wafer both control the silicate concentration in the etch bath to stable an etching selectivity with respect to silicon oxide and silicon nitride.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a semiconductor substrate, and a first gate stack formed over the semiconductor substrate and adjacent to the source/drain contact structure. The semiconductor device structure also includes an insulating cap structure formed over and separated from an upper surface of the first gate stack. In addition, the semiconductor device structure includes first gate spacers formed over opposing sidewalls of the first gate stack to separate the first gate stack from the source/drain contact structure. The first gate spacers extend over opposing sidewalls of the insulating cap structure, so as to form an air gap surrounded by the first gate spacers, the first gate stack, and the insulating cap structure.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.